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TI-LM3639A.pdf
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SCL
SDA
STROBE
TX
VIN
OUTF
GND
SWF
LM3639A
2.5V - 5.5V
SWB
VOUTB
up to 40V
COUTB
BLED2
BLED1
EN
CIN
L(F)
L(B)
Schottky
OVP
COUTF
FLED1FLED2
FLED1
FLED2
PWM
OR
LM3639A
www.ti.com.cn
ZHCSBI1 –MARCH 2013
LM3639A 单单芯芯片片 40V 背背光光 + 1.5A 闪闪光光发发光光二二级级管管 (LED) 驱驱动动器器
查查询询样样品品: LM3639A
1
特特性性
说说明明
2
• 单单芯芯片片白白光光 LED 闪闪光光和和背背光光驱驱动动器器
LM3639A 是一款单片白光 LED 摄像头闪光驱动器 +
LCD 显示器背光驱动器。 低电压、高电流的闪光 LED
• 1.5A 闪闪光光 LED 电电流流
驱动器是一款同步升压转换器,此转换器可为单个闪光
• 双双灯灯串串背背光光控控制制((V
输输出出
最最大大值值 40V))
LED 提供高达 1.5A 的电流,或为双 LED 的每个 LED
• 128 级级指指数数和和线线性性亮亮度度控控制制
提供高达 750mA 的电源。 高电压背光驱动器具有双
• 针针对对内内容容自自适适应应亮亮度度控控制制 (CABC) 的的脉脉宽宽调调制制
(PWM) 输输入入
输出异步升压功能,可为双 LED 灯串的每个灯串提供
• 可可编编程程过过压压保保护护((背背光光))
高达 40V 的电压和 30mA 的电流。 这两个升压转换器
中的自适应稳压方法规定了各自拉电流/灌电流中的净
• 可可编编程程电电流流限限制制((闪闪光光))
空电压,以便在尽可能提高效率的同时确保 LED 电流
• 可可编编程程开开关关频频率率
保持稳定。 LM3639A 的闪光驱动器是用于高电流白光
• 低低电电池池电电量量情情况况下下优优化化的的闪闪光光电电流流
LED 的 2MHz 或 4MHz 固定频率同步升压转换器及
应应用用范范围围
1.5A 恒定电流驱动器。 高侧电流源允许阴极接地 LED
• 白白光光 LED 背背光光显显示示器器电电源源
操作,从而提供高达 1.5A 的闪光电流。 自适应调节方
• 白白光光 LED 摄摄像像头头闪闪光光电电源源
法确保电流源保持可调节状态,并且大大提高了效率。
此器件由一个 I
2
C 兼容接口控制。 针对闪光 LED 驱动
器的特性包括一个可由逻辑输入触发闪光脉冲的硬件闪
光使能 (STROBE),和一个用于与射频 (RF) 功率放大
器事件或其他高电流情况同步的 TX 输入。 针对 LCD
背光驱动器的特性包括一个用于内容可调背光控制的
PWM 输入,128 个指数或线性亮度控制级,可编程过
压保护和可选开关频率(500kHz 至 1MHz)。
此器件采用微型 1.790mm x 2.165mm x 0.6mm 20 焊
锡凸点,0.4mm 焊球间距芯片级球栅阵列 (DSBGA)
封装,运行温度范围介于 -40°C 至 +85°C 之间。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not English Data Sheet: SNVS964
necessarily include testing of all parameters.
Top View
A B C D E
Bottom View
E D C B A
1
2
3
4
1
2
3
4
LM3639A
ZHCSBI1 –MARCH 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Connection Diagram
Figure 1. 20-Bump, 0.4 mm Pitch DSBGA Package
YFQ0020HGA
PIN DESCRIPTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
FLED1 A1 Output High Side Current Source Output for Flash LED1.
FLED2 B1 Output High Side Current Source Output for Flash LED2.
Flash LED Boost Output. Connect a 10 µF ceramic capacitor between this
OUTF (x2) A2/B2 Output
pin GND.
Drain Connection for Internal NMOS and Synchronous PMOS Switches.
SWF (x2) A3/B3 Output
Connect the Flash LED Boost Inductor to SWF.
GND (x3) A4/B4/E3 Ground
Power Amplifier Synchronization Input. The TX pin has a 300 kΩ pull-down
TX C2 Input
resistor connected to GND.
Active High Hardware Flash Enable. Drive STROBE high to turn on Flash
STROBE C3 Input pulse. STROBE overrides TORCH. The STROBE pin has a 300 kΩ pull-
down resistor connected to GND.
Input Voltage Connection. Connect IN to the input supply, and bypass to
VIN C4 Input
GND with a 10 µF or larger ceramic capacitor.
SDA D3 Input Serial Data Input/Output.
SCL D2 Input Serial Clock Input.
EN C1 Input Enable Pin. High = Standby, Low = Shutdown/Reset.
Drain Connection for internal NFET. Connect SWB to the junction of the
SWB E4 Input
backlight boost inductor and the Schottky diode anode.
PWM Brightness Control Input for backlight current control. The PWM pin
PWM D4 Input
has a 300 kΩ pull-down resistor connected to GND.
Input Terminal to Backlight LED String Current Sink #1 (40V max). The boost
BLED1 D1 Input
converter regulates the minimum of BLED1 and BLED2 to 400 mV.
Input Terminal to Backlight LED String Current Sink #2 (40V max). The boost
BLED2 E1 Input
converter regulates the minimum of BLED1 and BLED2 to 400 mV.
Over-Voltage Sense Input for Backlight Boost. Connect to the positive
OVP E2 Input
terminal of (COUTB).
2 Copyright © 2013, Texas Instruments Incorporated
LM3639A
www.ti.com.cn
ZHCSBI1 –MARCH 2013
ABSOLUTE MAXIMUM RATINGS
(1)
VIN
(2) (3)
−0.3V to 6V
−0.3V to the lesser of (V
IN
+0.3V) w/ 6V
SWF, OUTF, FLED1, FLED2, EN, PWM, SCL, SDA, TX, STROBE
(2)
max
SWB, OVP, BLED1, BLED2
(2)
−0.3V to +45V
Storage Temperature Range −65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics table.
(2) All voltages are with respect to the potential at the GND pin.
(3) V
IN
can be below −0.3V if the current out of the pin is limited to 500 µA.
OPERATING RATINGS
(1) (2)
V
IN
2.5V to 5.5V
Junction Temperature (T
J
) −40°C to +125°C
Ambient Temperature (T
A
)
(3)
−40°C to +85°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics table.
(2) All voltages are with respect to the potential at the GND pin.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating junction temperature (T
J-MAX-OP
=
+125°C), the maximum power dissipation of the device in the application (P
D-MAX
), and the junction-to-ambient thermal resistance of the
part/package in the application (θ
JA
), as given by the following equation: T
A-MAX
= T
J-MAX-OP
– (θ
JA
× P
D-MAX
).
THERMAL PROPERTIES
Thermal Junction-to-Ambient Resistance (θ
JA
)
(1)
48.8°C/W
(1) Junction-to-ambient thermal resistance (θ
JA
) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2 x 1 array
of thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36μm/18μm/18μm/36μm
(1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C in still air. Power dissipation is 1W. In applications where high
maximum power dissipation exists special care must be paid to thermal dissipation issues.
Copyright © 2013, Texas Instruments Incorporated 3
LM3639A
ZHCSBI1 –MARCH 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS
(1) (2)
Limits in standard typeface are for T
A
= +25°C. Limits in boldface type apply over the full operating ambient temperature
range (−40°C ≤ T
A
≤ +85°C). Unless otherwise specified, V
IN
= 3.6V.
Symbol Parameter Test Conditions Min Typ Max Unit
V
IN
Input Voltage Range 2.5 3.6 5.5 V
I
SHDN
Shutdown Supply Current Device Shutdown, EN = GND 1 3.5
µA
Device Disabled via I
2
C
I
SB
Standby Supply Current 1 4
EN = VIN
Low Voltage Boost Specifications (Flash Driver)
750 mA Flash
−7% 1.5 +7% A
Current Setting
28.125 mA Torch
I
FLED1
+ I
FLED2
Current Source Accuracy 2.7V ≤ V
IN
≤ 5.5V
Current Setting,
−10% 56.25 +10% mA
per current
source
For 750 mA Flash Current Setting 315
V
HR1
, V
HR2
Regulated Headroom Voltage mV
For 28.125 mA Torch Current Setting 180
ON Threshold 4.87 5 5.10
Output Over-Voltage
V
OVP
V
Protection Trip Point
OFF Threshold 4.71 4.88 4.98
R
PMOS
PMOS Switch On-Resistance I
PMOS
= 1A 85
mΩ
R
NMOS
NMOS Switch On-Resistance I
NMOS
= 1A 75
−12% 1.7 12%
−12% 1.9 12%
I
CL
Switch Current Limit V
IN
= 3.6V A
−12% 2.5 12%
−12% 3.1 12%
Input Voltage Monitor
V
IVM
V
IN
Falling −4% 2.5 4% V
Threshold
f
SW
Switching Frequency 2.5V ≤ V
IN
≤ 5.5V 3.64 4.00 4.36 MHz
Device Not Switching
IQ Quiescent Supply Current 0.6 2 mA
Pass Mode, Backlight Disabled
Flash to Torch LED Current TX low to High, ILED1,2 = 750 mA to
t
TX
4 µs
Settling Time 23.44 mA
High Voltage Boost Specification (Backlight Driver)
Output Current Regulation 2.7V ≤ V
IN
≤ 5.5V, Full Scale Current =
I
BLED1
, I
BLED2
−7% 19 7% mA
(BLED1 or BLED2) 19 mA, Brightness Register = 0xFF
BLED1 to BLED2 Current 2.7V ≤ V
IN
≤ 5.5V, Full Scale Current =
I
MATCH_HV
1 2.25 %
Matching
(3)
19 mA, Brightness Register = 0xFF
Regulated Current Sink
V
REG_CS
I
LED
= 19mA 400
Headroom Voltage
mV
Current Sink Minimum
V
HR_MIN
I
LED
= 95% of I
LED
= 19 mA 130
Headroom Voltage
R
DSON
NMOS Switch On Resistance I
SW
= 500 mA 230 mΩ
I
CL_BOOST
NMOS Switch Current Limit V
IN
= 3.6V −10% 1 10% A
ON Threshold, 2.7V ≤ VIN ≤ 5.5V,
38.4 40.0 41.4
Output Over-Voltage
OVP select bits = 11
V
OVP
V
Protection
Hysteresis 1
2.5V ≤ VIN ≤ 5.5V,
f
SW
Switching Frequency Boost Frequency 465 500 535 kHz
Select Bit = '0'
D
MAX
Maximum Duty Cycle 94 %
(1) All voltages are with respect to the potential at the GND pin.
(2) JESD ESD tests are applied at the ASIC level. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into
each pin. The machine model is a 200 pF capacitor discharged directly into each pin.
(3) Matching (%)= 100 × (|(ILED1 - ILED2 )| / (ILED1 + ILED2))
4 Copyright © 2013, Texas Instruments Incorporated
SDA
SDA
LM3639A
www.ti.com.cn
ZHCSBI1 –MARCH 2013
ELECTRICAL CHARACTERISTICS
(1) (2)
(continued)
Limits in standard typeface are for T
A
= +25°C. Limits in boldface type apply over the full operating ambient temperature
range (−40°C ≤ T
A
≤ +85°C). Unless otherwise specified, V
IN
= 3.6V.
Symbol Parameter Test Conditions Min Typ Max Unit
Logic Input Voltage Specifications (EN, STROBE, TORCH, TX, PWM)
V
IL
Input Logic Low 2.5V ≤ VIN ≤ 5.5V 0 0.4
V
V
IH
Input Logic High 2.5V ≤ VIN ≤ 5.5V 1.2 V
IN
Logic Input Voltage Specifications (SCL, SDA)
V
OL
Output Logic Low (SDA only) I
LOAD
= 3 mA 400 mV
V
IL
Input Logic Low 2.5V ≤ VIN ≤ 5.5V 0 0.4
V
V
IH
Input Logic High 2.5V ≤ VIN ≤ 4.2V 1.2 V
IN
I
2
C-Compatible Timing Specifications (SCL, SDA)
1/t1 SCL (Clock Frequency) kHz
Data In Setup Time to SCL
t2 100
High
Data Out Stable After SCL
t3 0
Low
ns
SDA Low Setup Time to SCL
t4 100
Low (Start)
SDA High Hold Time After
t5 100
SCL High (Stop)
Figure 2. I
2
C Timing Diagram
Copyright © 2013, Texas Instruments Incorporated 5
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