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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5109A

SNVS412C –APRIL 2006–REVISED SEPTEMBER 2016

LM5109A High Voltage 1A Peak Half Bridge Gate Driver

1 Features

• Drives Both a High-Side and Low-Side N-Channel

MOSFET

• 1A peak Output Current (1.0A Sink / 1.0A Source)

• Independent TTL Compatible Inputs

• Bootstrap Supply Voltage to 108V DC

• Fast Propagation Times (30 ns Typical)

• Drives 1000 pF Load with 15ns Rise and Fall

Times

• Excellent Propagation Delay Matching (2 ns

Typical)

• Supply Rail Under-Voltage Lockout

• Low Power Consumption

• Pin Compatible with ISL6700

• Industry Standard SOIC-8 and Thermally

Enhanced WSON-8 Package

2 Applications

• Current Fed Push-Pull Converters

• Half and Full Bridge Power Converters

• Solid State Motor Drives

• Two Switch Forward Power Converters

3 Description

The LM5109A is a cost effective, high voltage gate

driver designed to drive both the high-side and the

low-side N-Channel MOSFETs in a synchronous

buck or a half bridge configuration. The floating high-

side driver is capable of working with rail voltages up

to 90V. The outputs are independently controlled with

TTL compatible input thresholds. The robust level

shift technology operates at high speed while

consuming low power and providing clean level

transitions from the control input logic to the high-side

gate driver. Under-voltage lockout is provided on both

the low-side and the high-side power rails. The

device is available in the SOIC and the thermally

enhanced WSON packages.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM5109A

SOIC (8) 4.90 mm × 3.91 mm

WSON (8) 4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Simplified Application Diagram

LM5109A

SNVS412C –APRIL 2006–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: LM5109A

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 3

6.1 Absolute Maximum Ratings ...................................... 3

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 4

6.6 Switching Characteristics.......................................... 5

6.7 Typical Performance Characteristics ........................ 6

7 Detailed Description.............................................. 8

7.1 Overview ................................................................... 8

7.2 Functional Block Diagram ......................................... 8

7.3 Feature Description................................................... 8

7.4 Device Functional Modes.......................................... 9

8 Application and Implementation ........................ 10

8.1 Application Information............................................ 10

8.2 Typical Application ................................................. 11

9 Power Supply Recommendations...................... 15

10 Layout................................................................... 16

10.1 Layout Guidelines ................................................. 16

10.2 Layout Example .................................................... 16

11 Device and Documentation Support ................. 17

11.1 Documentation Support ........................................ 17

11.2 Receiving Notification of Documentation Updates 17

11.3 Community Resource............................................ 17

11.4 Trademarks ........................................................... 17

11.5 Electrostatic Discharge Caution............................ 17

11.6 Glossary ................................................................ 17

12 Mechanical, Packaging, and Orderable

Information ........................................................... 17

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (March 2016) to Revision C Page

• Updated values in the Thermal Information table to align with JEDEC standards................................................................. 4

• Added Overview section......................................................................................................................................................... 8

• Added Feature Description section. ....................................................................................................................................... 8

• Added Device Functional Modes section. .............................................................................................................................. 9

• Added Typical Application section........................................................................................................................................ 11

• Added Power Supply Recommendations section. .............................................................................................................. 15

Changes from Revision A (March 2013) to Revision B Page

• Added Device Information table, ESD Ratings, Pin Configuration and Functions section, Detailed Description

section, Application and Implementation section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1

Changes from Original (March 2013) to Revision A Page

• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 10

LM5109A

www.ti.com

SNVS412C –APRIL 2006–REVISED SEPTEMBER 2016

Product Folder Links: LM5109A

5 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

NGT Package

8-Pin WSON

Top View

(1) For WSON package it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB

and the ground plane should extend out from underneath the package to improve heat dissipation.

Pin Functions

Pin #

NAME DESCRIPTION APPLICATION INFORMATION

SOIC WSON

(1)

1 1 V

Positive gate drive supply

Locally decouple to V

using low ESR/ESL capacitor located as

close to IC as possible.

2 2 HI High side control input

The HI input is compatible with TTL input thresholds. Unused HI input

should be tied to ground and not left open

3 3 LI Low side control input

The LI input is compatible with TTL input thresholds. Unused LI input

should be tied to ground and not left open.

4 4 V

Ground reference All signals are referenced to this ground.

5 5 LO Low side gate driver output Connect to the gate of the low-side N- MOS device.

6 6 HS High side source connection

Connect to the negative terminal of the bootstrap capacitor and to the

source of the high-side N-MOS device.

7 7 HO High side gate driver output Connect to the gate of the high-side N-MOS device.

8 8 HB

High side gate driver positive

supply rail

Connect the positive terminal of the bootstrap capacitor to HB and

the negative terminal of the bootstrap capacitor to HS. The bootstrap

capacitor should be placed as close to IC as possible.

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test

conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally

not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated

voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than V

– 15V. For example, if

= 10V, the negative transients at HS must not exceed –5V.

6 Specifications

6.1 Absolute Maximum Ratings

See

(1)(2)

MIN MAX UNIT

to V

–0.3 18 V

HB to HS −0.3 18 V

LI or HI to V

−0.3 V

+ 0.3 V

LO to V

−0.3 V

+ 0.3 V

HO to V

− 0.3 V

+ 0.3 V

HS to V

(3)

−5 90 V

HB to V

108 V

Junction Temperature –40 150 °C

Storage Temperature Range −55 150 °C

LM5109A

SNVS412C –APRIL 2006–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: LM5109A

(1) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.

6.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge Human-body model (HBM)

(1)

±1500 V

(1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally

not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated

voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than V

– 15V. For example, if

= 10V, the negative transients at HS must not exceed –5V.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT

8 14 V

(1)

−1 90 V

HB V

+ 8 V

+ 14 V

HS Slew Rate < 50 V/ns

Junction Temperature −40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC

(1)

LM5109A

UNITD (SOIC) NGT (WSON)

8 PINS 8 PINS

θJA

Junction-to-ambient thermal resistance 117.6 42.3 °C/W

θJC(top)

Junction-to-case (top) thermal resistance 64.9 34 °C/W

θJB

Junction-to-board thermal resistance 58.1 19.3 °C/W

Junction-to-top characterization parameter 17.4 0.4 °C/W

Junction-to-board characterization parameter 57.6 19.5 °C/W

θJC(bot)

Junction-to-case (bottom) thermal resistance – 8.1 °C/W

(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through

correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

6.5 Electrical Characteristics

Unless otherwise specified, V

= V

= 12V, V

= V

= 0V, No Load on LO or HO

(1)

. Typical limits are for T

= 25°C, and

minimum and maximum limits apply over the operating junction temperature range (–40°C to 125°C).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENTS

quiescent current LI = HI = 0V 0.3 0.6 mA

DDO

operating current f = 500 kHz 1.8 2.9 mA

Total HB quiescent current LI = HI = 0V 0.06 0.2 mA

HBO

Total HB operating current f = 500 kHz 1.4 2.8 mA

HBS

HB to V

current, quiescent V

= V

= 90V 0.1 10 µA

HBSO

HB to V

current, operating f = 500 kHz 0.5 mA

INPUT PINS LI and HI

Low-level input voltage threshold 0.8 1.8 V

High-level input voltage threshold 1.8 2.2 V

Input pulldown resistance 100 200 500 kΩ

UNDER-VOLTAGE PROTECTION

DDR

rising threshold V

DDR

= V

– V

6.0 6.7 7.4 V

DDH

threshold hysteresis 0.5 V

HBR

HB rising threshold V

HBR

= V

– V

5.7 6.6 7.1 V

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