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TI-LM5100A.pdf
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LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
LM5100A/B/C, LM5101A/B/C 3-A, 2-A, and 1-A High-Voltage, High-Side
and Low-Side Gate Drivers
An integrated high-voltage diode is provided to
1 Features
charge the high-side gate drive bootstrap capacitor. A
1
• Drives Both a High-Side and Low-Side N-Channel
robust level shifter operates at high speed while
MOSFETs
consuming low power and providing clean level
• Independent High- and Low-Driver Logic Inputs
transitions from the control logic to the high-side gate
driver. Undervoltage lockout is provided on both the
• Bootstrap Supply Voltage up to 118 V DC
low-side and the high-side power rails. These devices
• Fast Propagation Times (25-ns Typical)
are available in the standard SOIC-8 pin, SO
• Drives 1000-pF Load With 8-ns Rise and Fall
PowerPAD-8 pin, and the WSON-10 pin packages.
Times
The LM5100C and LM5101C are also available in
MSOP-PowerPAD-8 package. The LM5101A is also
• Excellent Propagation Delay Matching (3-ns
available in WSON-8 pin package.
Typical)
• Supply Rail Undervoltage Lockout
Device Information
(1)
• Low Power Consumption
PEAK OUTPUT
PART NUMBER INPUT THRESHOLD
CURRENT
• Pin Compatible With HIP2100/HIP2101
LM5100A CMOS 3 A
2 Applications
LM5101A TTL 3 A
LM5100B CMOS 2 A
• Current-Fed Push-Pull Converters
LM5101B TTL 2 A
• Half and Full Bridge Power Converters
LM5100C CMOS 1 A
• Synchronous Buck Converters
LM5101C TTL 1 A
• Two Switch Forward Power Converters
(1) For all available packages, see the orderable addendum at
• Forward with Active Clamp Converters
the end of the data sheet.
3 Description
The LM5100A/B/C and LM5101A/B/C high-voltage
gate drivers are designed to drive both the high-side
and the low-side N-Channel MOSFETs in a
synchronous buck or a half-bridge configuration. The
floating high-side driver is capable of operating with
supply voltages up to 100 V. The A versions provide
a full 3-A of gate drive, while the B and C versions
provide 2 A and 1 A, respectively. The outputs are
independently controlled with CMOS input thresholds
(LM5100A/B/C) or TTL input thresholds
(LM5101A/B/C).
Simplified Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
Table of Contents
8.3 Feature Description................................................. 14
1 Features.................................................................. 1
8.4 Device Functional Modes........................................ 15
2 Applications ........................................................... 1
9 Application and Implementation ........................ 16
3 Description ............................................................. 1
9.1 Application Information............................................ 16
4 Revision History..................................................... 2
9.2 Typical Application ................................................. 16
5 Device Comparison Table..................................... 3
10 Power Supply Recommendations ..................... 20
6 Pin Configuration and Functions......................... 3
11 Layout................................................................... 21
7 Specifications......................................................... 5
11.1 Layout Guidelines ................................................. 21
7.1 Absolute Maximum Ratings ..................................... 5
11.2 Layout Example .................................................... 21
7.2 ESD Ratings.............................................................. 5
12 Device and Documentation Support ................. 22
7.3 Recommended Operating Conditions....................... 5
12.1 Documentation Support ....................................... 22
7.4 Thermal Information.................................................. 6
12.2 Related Links ........................................................ 22
7.5 Electrical Characteristics ......................................... 6
12.3 Community Resources.......................................... 22
7.6 Switching Characteristics......................................... 8
12.4 Trademarks........................................................... 22
7.7 Typical Characteristics............................................ 10
12.5 Electrostatic Discharge Caution............................ 22
8 Detailed Description............................................ 14
12.6 Glossary................................................................ 22
8.1 Overview ................................................................. 14
13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 14
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (March 2013) to Revision Q Page
• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
Changes from Revision O (March 2013) to Revision P Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 19
2 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
Exposed Pad
Connect to VSS
HO
3
HS
4
VDD
1
HB
2
8
LO
7
VSS
6
LI
5
HI
SO
PowerPad-8
WSON-8
1
2
3
4 5
6
7
8VDD
HB
HO
HS HI
LI
VSS
LO
WSON-10
1
2
3
4
9
6
7
8
VDD
HB
HO
HS HI
LI
VSS
LO
NC
5
10
NC
VDD
HB
HO
HS
LO
VSS
LI
HI
1
8
2
7
3
6
4 5
SOIC-8
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
5 Device Comparison Table
PART NUMBER PACKAGE BODY SIZE (NOM)
WSON (10) 4.00 mm × 4.00 mm
LM5100A, LM5100C SO PowerPAD™ (8) 3.90 mm × 4.89 mm
SOIC (8) 3.91 mm × 4.90 mm
WSON (10) 4.00 mm × 4.00 mm
LM5100B, LM5101B
SOIC (8) 3.91 mm × 4.90 mm
WSON (8) 4.00 mm × 4.00 mm
WSON (10) 4 .00mm × 4.00 mm
LM5101A
SO PowerPAD (8) 3.90 mm × 4.89 mm
SOIC (8) 3.91 mm × 4.90 mm
MSOP PowerPAD (8) 3.00 mm × 3.00 mm
LM5101C WSON (10) 4.00 mm × 4.00 mm
SOIC (8) 3.91 mm × 4.90 mm
6 Pin Configuration and Functions
D Package
DPR Package
8-Pin SOIC
10-Pin WSON With Exposed Thermal Pad
Top View
Top View
NGT Package
8-Pin WSON With Exposed Thermal Pad
DDA Package
Top View
8-Pin SO PowerPAD
Top View
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
VDD
HB
HO
HS
LO
VSS
LI
HI
MSOP-
PowerPad-8
1
2
3
4 5
6
7
8
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
DGN Package
8-Pin MSOP-PowerPAD
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME 8 PINS 10 PINS
(1)
High-side gate driver bootstrap supply. Connect the positive terminal of the bootstrap
HB 2 2 I capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be
placed as close to the IC as possible.
High-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
HI 5 7 I The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
High-side gate driver output. Connect to the gate of high-side MOSFET with a short,
HO 3 3 O
low inductance path.
High-side MOSFET source connection. Connect to the bootstrap capacitor negative
HS 4 4 —
terminal and the source of the high-side MOSFET.
Low-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
LI 6 8 I The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
Low-side gate driver output. Connect to the gate of the low-side MOSFET with a
LO 8 10 O
short, low inductance path.
Positive gate drive supply . Locally decouple to VSS using low ESR/ESL capacitor
VDD 1 1 I
located as close to the IC as possible.
VSS 7 9 — Ground return. All signals are referenced to this ground.
TI recommends that the exposed pad on the bottom of the package is soldered to
EP
(2)
— ground plane on the PC board, and that ground plane should extend out from
beneath the IC to help dissipate heat.
(1) For WSON-10 package, pins 5 and 6 have no connection.
(2) Exposed pad is not available on the 8-pin SOIC package.
4 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
See
(1)(2)
MIN MAX UNIT
VDD to VSS −0.3 18 V
HB to HS −0.3 18 V
LI or HI input −0.3 V
DD
+ 0.3 V
LO output −0.3 V
DD
+ 0.3 V
HO output V
HS
− 0.3 V
HB
+ 0.3 V
HS to VSS
(3)
−5 100 V
HB to VSS 118 V
Junction temperature 150 °C
Storage temperature −55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military or Aerospace specified devices are required, contact the Texas Instruments Sales Office or Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not
exceed – 1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage
transiently. If negative transients occur, the HS voltage must never be more negative than VDD – 15 V. For example if VDD = 10 V, the
negative transients at HS must not exceed –5 V.
7.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Electrostatic
V
(ESD)
Option A 50 V
discharge
Machine Model (MM)
(2)
Option B and C 100
(1) The Human Body Model (HBM) is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2 kV for all pins except Pin 2,
Pin 3 and Pin 4 which are rated at 1000 V for HBM.
(2) Machine Model (MM) ratings are: 100 V(MM) for Options B and C; 50 V(MM) for Option A.
7.3 Recommended Operating Conditions
MIN NOM MAX UNIT
VDD 9 14 V
HS –1 100 V
HB V
HS
+ 8 V
HS
+ 14 V
HS slew rate < 50 V/ns
Junction temperature −40 125 °C
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
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