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TI-LM5109B.pdf
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LM5109B
SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016
LM5109B High Voltage 1-A Peak Half-Bridge Gate Driver
1 Features 3 Description
The LM5109B device is a cost-effective, high-voltage
1
• Drives Both a High-Side and Low-Side N-Channel
gate driver designed to drive both the high-side and
MOSFET
the low-side N-channel MOSFETs in a synchronous
• 1-A Peak Output Current (1.0-A Sink and 1.0-A
buck or a half-bridge configuration. The floating
Source)
high-side driver is capable of working with rail
voltages up to 90 V. The outputs are independently
• Inputs Compatible With Independent TTL and
controlled with cost-effective TTL and
CMOS
CMOS-compatible input thresholds. The robust level
• Bootstrap Supply Voltage to 108-V DC
shift technology operates at high speed while
• Fast Propagation Times (30 ns Typical)
consuming low power and providing clean level
• Drives 1000-pF Load With 15-ns Rise and Fall transitions from the control input logic to the high-side
gate driver. Undervoltage lockout is provided on both
Times
the low-side and the high-side power rails. The
• Excellent Propagation Delay Matching (2 ns
device is available in the 8-pin SOIC and thermally-
Typical)
enhanced 8-pin WSON packages.
• Supply Rail Undervoltage Lockout
Device Information
(1)
• Low Power Consumption
PART NUMBER PACKAGE BODY SIZE (NOM)
• 8-Pin SOIC and Thermally-Enhanced 8-Pin
SOIC (8) 4.90 mm × 3.91 mm
WSON Package
LM5109B
WSON (8) 4.00 mm × 4.00 mm
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Current-Fed, Push-Pull Converters
• Half- and Full-Bridge Power Converters
• Solid-State Motor Drives
• Two-Switch Forward Power Converters
Simplified Application Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5109B
SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 10
1 Features.................................................................. 1
7.5 HS Transient Voltages Below Ground .................... 10
2 Applications ........................................................... 1
8 Application and Implementation ........................ 11
3 Description ............................................................. 1
8.1 Application Information............................................ 11
4 Revision History..................................................... 2
8.2 Typical Application ................................................. 11
5 Pin Configuration and Functions......................... 3
9 Power Supply Recommendations...................... 15
6 Specifications......................................................... 4
10 Layout................................................................... 16
6.1 Absolute Maximum Ratings ...................................... 4
10.1 Layout Guidelines ................................................. 16
6.2 ESD Ratings.............................................................. 4
10.2 Layout Example .................................................... 16
6.3 Recommended Operating Conditions....................... 4
11 Device and Documentation Support ................. 17
6.4 Thermal Information.................................................. 5
11.1 Documentation Support ........................................ 17
6.5 Electrical Characteristics........................................... 5
11.2 Community Resources.......................................... 17
6.6 Switching Characteristics.......................................... 6
11.3 Trademarks........................................................... 17
6.7 Typical Characteristics.............................................. 7
11.4 Electrostatic Discharge Caution............................ 17
7 Detailed Description.............................................. 9
11.5 Glossary................................................................ 17
7.1 Overview ................................................................... 9
12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ......................................... 9
Information ........................................................... 17
7.3 Feature Description................................................... 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2013) to Revision C Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision A (March 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format ............................................................................................................. 1
2 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: LM5109B
HI
LI
V
SS
HO
HS
LO
HB
V
DD
WSON-8
1
2
3
4
8
7
6
5
HI
LI
V
SS
HO
HS
LO
HB
V
DD
SOIC-8
1
2
3
4
8
7
6
5
LM5109B
www.ti.com
SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
NGT Package
8-Pin WSON
Top View
Pin Functions
PIN
DESCRIPTION
NO.
(1)
NAME TYPE
(2)
Positive gate drive supply – Locally decouple to V
SS
using low ESR and ESL capacitor located
1 V
DD
P
as close to IC as possible.
High-side control input – The HI input is compatible with TTL and CMOS input thresholds.
2 HI I
Unused HI input must be tied to ground and not left open.
Low-side control input – The LI input is compatible with TTL and CMOS input thresholds.
3 LI I
Unused LI input must be tied to ground and not left open.
4 V
SS
G Ground – All signals are referenced to this ground.
5 LO O Low-side gate driver output – Connect to the gate of the low-side N-MOS device.
High-side source connection – Connect to the negative terminal of the bootstrap capacitor and
6 HS P
to the source of the high-side N-MOS device.
7 HO O High-side gate driver output – Connect to the gate of the high-side N-MOS device.
High-side gate driver positive supply rail – Connect the positive terminal of the bootstrap
8 HB P capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap
capacitor must be placed as close to IC as possible.
(1) For 8-pin WSON package, TI recommends that the exposed pad on the bottom of the package be soldered to ground plane on the PCB
and the ground plane must extend out from underneath the package to improve heat dissipation.
(2) G = Ground, I = Input, O = Output, and P = Power
Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM5109B
LM5109B
SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
V
DD
to V
SS
–0.3 18 V
HB to HS –0.3 18 V
LI or HI to V
SS
–0.3 V
DD
+ 0.3 V
LO to V
SS
–0.3 V
DD
+ 0.3 V
HO to V
SS
V
HS
– 0.3 V
HB
+ 0.3 V
HS to V
SS
(2)
–5 90 V
HB to V
SS
108 V
Junction temperature –40 150 °C
Storage temperature, T
stg
–55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than V
DD
– 15 V. For example, if
V
DD
= 10 V, the negative transients at HS must not exceed –5 V.
6.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±1500
V
(ESD)
Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
DD
8 14 V
HS
(1)
–1 90 V
HB V
HS
+ 8 V
HS
+ 14 V
HS slew rate 50 V/ns
Junction temperature –40 125 °C
(1) In the application, the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than V
DD
– 15 V. For example, if
V
DD
= 10 V, the negative transients at HS must not exceed –5 V.
4 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: LM5109B
LM5109B
www.ti.com
SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016
6.4 Thermal Information
LM5109B
THERMAL METRIC
(1)
D (SOIC) NGT (WSON) UNIT
8 PINS 8 PINS
R
θJA
Junction-to-ambient thermal resistance 117.6 42.3 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 64.9 34.0 °C/W
R
θJB
Junction-to-board thermal resistance 58.1 19.3 °C/W
ψ
JT
Junction-to-top characterization parameter 17.4 0.4 °C/W
ψ
JB
Junction-to-board characterization parameter 57.6 19.5 °C/W
R
θJC(bot)
Junction-to-case (bottom) thermal resistance – 8.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
T
J
= 25°C (unless otherwise specified), V
DD
= V
HB
= 12 V, V
SS
= V
HS
= 0 V, No Load on LO or HO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
T
J
= 25°C 0.3
I
DD
V
DD
quiescent current LI = HI = 0 V mA
T
J
= –40°C to 125°C 0.6
T
J
= 25°C 1.8
I
DDO
V
DD
operating current f = 500 kHz mA
T
J
= –40°C to 125°C 2.9
T
J
= 25°C 0.06
I
HB
Total HB quiescent current LI = HI = 0 V mA
T
J
= –40°C to 125°C 0.2
T
J
= 25°C 1.4
I
HBO
Total HB operating current f = 500 kHz mA
T
J
= –40°C to 125°C 2.8
T
J
= 25°C 0.1
I
HBS
HB to V
SS
current, quiescent V
HS
= V
HB
= 90 V µA
T
J
= –40°C to 125°C 10
I
HBSO
HB to V
SS
current, operating f = 500 kHz 0.5 mA
INPUT PINS LI AND HI
T
J
= 25°C 1.8
V
IL
Low level input voltage threshold V
T
J
= –40°C to 125°C 0.8
T
J
= 25°C 1.8
V
IH
High level input voltage threshold V
T
J
= –40°C to 125°C 2.2
T
J
= 25°C 200
R
I
Input pulldown resistance kΩ
T
J
= –40°C to 125°C 100 500
UNDERVOLTAGE PROTECTION
T
J
= 25°C 6.7
V
DDR
V
DD
rising threshold V
DDR
= V
DD
– V
SS
V
T
J
= –40°C to 125°C 6.0 7.4
V
DDH
V
DD
threshold hysteresis 0.5 V
T
J
= 25°C 6.6
V
HBR
HB rising threshold V
HBR
= V
HB
– V
HS
V
T
J
= –40°C to 125°C 5.7 7.1
V
HBH
HB threshold hysteresis 0.4 V
LO GATE DRIVER
T
J
= 25°C 0.38
V
OLL
Low-level output voltage I
LO
= 100 mA, V
OHL
= V
LO
– V
SS
V
T
J
= –40°C to 125°C 0.65
T
J
= 25°C 0.72
V
OHL
High-level output voltage I
LO
= −100 mA, V
OHL
= V
DD
– V
LO
V
T
J
= –40°C to 125°C 1.2
I
OHL
Peak pullup current V
LO
= 0 V 1 A
I
OLL
Peak pulldown current V
LO
= 12 V 1 A
Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM5109B
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