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TI-UCD90124.pdf
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TI-UCD90124.pdf
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Vmarg
Closed Loop
Margining
UCD90124
VMON
GPIO
12V
V33FB
V33A
V33D
GPIO
3.3V OUT
VMON
1.8V OUT
3.3V_UCD
0.8V OUT
I0.8V
TEMP0.8V
VMON
VMON
VMON
VMON
I12V
TEMP12V
VMON
VMON
INA196
I12V
12V OUT
3.3V OUT
12V OUT
1.8V OUT
GPIO
GPIO
0.8V OUT
PWM
2MHz
INA196
I0.8V
WDI from main
processor
GPIO
WDO
GPIO
TEMP IC
TEMP0.8V
TEMP IC
TEMP12V
POWER_GOOD
GPIO
WARN_OC_0.8V_
OR_12V
GPIO
SYSTEM RESET
GPIO
OTHER
SEQUENCER DONE
(CASCADE INPUT)
GPIO
I2C/
PMBUS
JT
AG
/EN
DC-DC 1
VOUT
VFB
VIN
/EN
LDO1
VOUT
VIN
/EN
DC-DC 2
VOUT
VFB
VIN
V
4- wire Fan
12 V
4-
DC Fan
PWM
GPIO
Fan T
ach
25 kHz Fan PWM
12V
T
ACH
PWM
GND
5.1V
UCD90124
www.ti.com
SLVSA29B –NOVEMBER 2009–REVISED SEPTEMBER 2010
12-Rail Sequencer and System Health Monitor With Fan Control
Check for Samples: UCD90124
1
FEATURES
DESCRIPTION
2
• Monitor and Sequence 12 Voltage Rails
– All Rails Sampled Every 400 ms
The UCD90124 is a 12-rail PMBus/I
2
C addressable
power-supply sequencer and system-health
– 12-bit ADC With 2.5-V, 0.5% Internal V
REF
monitor. The device integrates a 12-bit ADC for
– Sequence Based on Time, Rail and Pin
monitoring up to 13 power-supply voltage, current, or
Dependencies
temperature inputs. Twenty-six GPIO pins can be
– Four Programmable Undervoltage and used for power supply enables, power-on reset
signals, external interrupts, cascading, or other
Overvoltage Thresholds per Monitor
system functions. Twelve of these pins offer PWM
• Fan Control and Monitoring
functionality. Using these pins, the UCD90124 offers
– Supports Four Fans With Five User-Defined
support for fan control, margining, and
Speed-vs-Temperature Setpoints
general-purpose PWM functions.
– Supports Two-, Three-, and Four-Wire Fans
Fan-control signals can be sent using PMBus
• Nonvolatile Error and Peak-Value Logging per
commands or generated from one of two built-in
Monitor (up to 10 Fault Detail Entries)
fan-control algorithms. PWM outputs combined with
temperature and fan-speed measurements provide a
• Closed-Loop Margining for 10 Rails
complete fan-control solution for up to four
– Margin Output Adjusts Rail Voltage to
independent fans.
Match User-Defined Margin Thresholds
The TI Fusion Digital Power™ designer software is
• Programmable Watchdog Timer and System
provided for device configuration. This PC-based
Reset
graphical user interface (GUI) offers an intuitive
• Flexible Digital I/O Configuration
interface for configuring, storing, and monitoring all
system operating parameters.
• Multiphase PWM Clock Generator
– Clock Frequencies From 15.259 kHz to 125
MHz
– Capability to Configure Independent Clock
Outputs for Synchronizing Switch-Mode
Power Supplies
• Internal Temperature Sensor
• JTAG and I
2
C/SMBus/ PMBus™ Interfaces
APPLICATIONS
• Industrial / ATE
• Telecommunications and Networking
Equipment
• Servers and Storage Systems
• Embedded Computing
• Any System Requiring Sequencing and
Monitoring of Multiple Power Rails
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PMBus, Fusion Digital Power are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Comparators
Monitor
Inputs
12-bit
ADC
(0.5% Int. Ref)
SEQUENCING ENGINE
BOOLEAN
L
ogic Builder
Internal
Temperature
Sensor
JTAG
Or
GPIO
I2C/
PMBus
FLASH Memory
U
ser Data, Fault
and Peak Logging
13
6
64-pin QFN
M
argining Outputs (10 max)
GPIO Capability
PWM
Fan Control (4 max)
14
12
G
eneral Purpose I/O
(GPIO)
Fan Tach Monitors (4 max)
Digital Inputs (8 max)
Digital Outputs (12 max)
Rail Enables (12 max)
Multi-phase PWM (8 max)
UCD90124
SLVSA29B –NOVEMBER 2009–REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see
the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
VALUE UNIT
Voltage applied at V33D to DV
SS
–0.3 V to 3.8 V
Voltage applied at V33A to AV
SS
–0.3 V to 3.8 V
Voltage applied at V33FB to AV
SS
–0.3 V to 5.5 V
Voltage applied to any other pin
(2)
–0.3 V to (V33A + V
0.3 V)
Storage temperature (T
stg
) –55 to 150 °C
Human-body model (HBM) 2.5 kV
ESD rating
Charged-device model (CDM) 750 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :UCD90124
UCD90124
www.ti.com
SLVSA29B –NOVEMBER 2009–REVISED SEPTEMBER 2010
THERMAL INFORMATION
UCD90124
THERMAL METRIC
(1)
RGC UNITS
64 PINS
q
JA
Junction-to-ambient thermal resistance
(2)
26.4
q
JC(top)
Junction-to-case(top) thermal resistance
(3)
21.2
q
JB
Junction-to-board thermal resistance
(4)
1.7
°C/W
y
JT
Junction-to-top characterization parameter
(5)
0.7
y
JB
Junction-to-board characterization parameter
(6)
8.8
q
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Supply voltage during operation (V
33D
, V
33DIO
, V
33A
) 3 3.3 3.6 V
Operating free-air temperature range, T
A
–40 110 °C
Junction temperature, T
J
125 °C
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s) :UCD90124
UCD90124
SLVSA29B –NOVEMBER 2009–REVISED SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
SUPPLY CURRENT
I
V33A
V
V33A
= 3.3 V 8 mA
I
V33DIO
V
V33DIO
= 3.3 V 2 mA
Supply current
(1)
I
V33D
V
V33D
= 3.3 V 40 mA
V
V33D
= 3.3 V, storing configuration parameters
I
V33D
50 mA
in flash memory
INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS
V
V33
3.3-V linear regulator Emitter of NPN transistor 3.25 3.3 3.35 V
V
V33FB
3.3-V linear reg feedback 4 4.6 V
I
V33FB
Series pass base drive V
VIN
= 12 V 10 mA
Beta Series NPN pass device 40
EXTERNALLY SUPPLIED 3.3V POWER
V
V33D
,
Digital 3.3-V power T
A
= 25°C 3 3.6 V
V
V33DIO
V
V33A
Analog 3.3-V power T
A
= 25°C 3 3.6 V
ANALOG INPUTS (MON1–MON13)
V
MON
Input voltage range MON1–MON9 0 2.5 V
MON10–MON13 0.2 2.5 V
INL ADC integral nonlinearity –2.5 2.5 mV
I
lkg
Input leakage current 3 V applied to pin 100 nA
I
OFFSET
Input offset current 1-kΩ source impedance –5 5 mA
MON1–MON9, ground reference 8 MΩ
R
IN
Input impedance
MON10–MON13, ground reference 0.5 1.5 3 MΩ
C
IN
Input capacitance 10 pF
t
CONVERT
ADC sample period 14 voltages sampled, 3.89 msec/sample 400 msec
ADC 2.5 V, internal reference 0°C to 125°C –0.5 0.5 %
V
REF
accuracy
–40°C to 125°C –1 1 %
ANALOG INPUT (PMBUS_ADDRx, INTERNAL TEMP SENSE)
I
BIAS
Bias current for PMBus Addr pins 9 11 mA
V
ADDR_OPEN
Voltage – open pin PMBus_ADDR0, PMBus_ADDR1 open 2.26 V
V
ADDR_SHORT
Voltage – shorted pin PMBus_ADDR0, PMBus_ADDR1 short to 0.124 V
ground
Internal temperature-sense
T
Internal
Over range from 0°C to 100°C –5 5 °C
accuracy
DIGITAL INPUTS AND OUTPUTS
V
OL
Low-level output voltage I
OL
= 6 mA
(2)
, V
33DIO
= 3 V Dgnd + V
0.25
V
OH
High-level output voltage I
OH
= –6 mA
(3)
, V
33DIO
= 3 V V
33DIO
V
– 0.6V
V
IH
High-level input voltage V
33DIO
= 3 V 2.1 3.6 V
V
IL
Low-level input voltage V
33DIO
= 3.5 V 1.4 V
(1) Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins.
(2) The maximum total current, I
OL
max, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
(3) The maximum total current, I
OH
max, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
4 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :UCD90124
UCD90124
www.ti.com
SLVSA29B –NOVEMBER 2009–REVISED SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
FAN CONTROL INPUTS AND OUTPUTS
FPWM1-8 15.259 125000
PWM1 10
T
PWM_FREQ
FAN-PWM frequency kHz
PWM2 1
PWM3-4 0.001 7800
DUTY
PWM
FAN-PWM duty cycle range 0 100 %
Tach
RANGE
FAN-TACH range For 1 Tach pulse per revolution. At 2, 3 or 4 30 300k RPM
pulse/rev, divide by the value
Tach
RES
FAN-TACH resolution For 1 Tach pulse per revolution 30 RPM
t
MIN
FAN-TACH minimum pulse width Either positive or negarive polarity 200 µs
MARGINING OUTPUTS
T
PWM_FREQ
MARGINING-PWM frequency FPWM1-8 15.260 125000 kHz
PWM3-4 0.001 7800
DUTY
PWM
MARGINING-PWM duty cycle range 0 100 %
SYSTEM PERFORMANCE
V
DD
Slew Minimum V
DD
slew rate V
DD
slew rate between 2.3 V and 2.9 V 0.25 V/ms
Supply voltage at which device
V
RESET
For power-on reset (POR) 2.4 V
comes out of reset
Low-pulse duration needed at
t
RESET
To reset device during normal operation 2 mS
RESET pin
f(PCLK) Internal oscillator frequency T
A
= 125°C, T
A
= 25°C 240 250 260 MHz
Retention of configuration
t
retention
T
J
= 25°C 100 Years
parameters
Number of nonvolatile erase/write
Write_Cycles T
J
= 25°C 20 K cycles
cycles
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s) :UCD90124
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