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TI-UCD9080.pdf
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TI-UCD9080.pdf
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1
FEATURES APPLICATIONS
DESCRIPTION
UCD 9080
EN[1:7]
SDA
SCL
VCC
VSS
MON [1:8]
A1
ROSC
RST
XIN
TEST
10kW
100kW
10kW
10kW
3.3 V
3.3 V 3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
0.01 Fm
1 Fm
A2
A3
A4
EN
EN
EN
V
OUT1
V
OUTX
V
OUT2
SlaveI C
Address
2
ToI C
2
MasterDevice
Digital
Outputs
EN8/
ADDR1/
GPO1
ADDR2/
GPO2
ADDR3/
GPO3
ADDR4/
GPO4
Power
Supply
1
Power
Supply
2
Power
Supply
X
UCD9080
www.ti.com
................................................................................................................................................... SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008
8-CHANNEL POWER-SUPPLY SEQUENCER AND MONITOR
• Telecommunications Switches
234
• Single Supply Voltage: 3.3 V
• Servers
• Low Power Consumption
• Networking Equipment
• Sequences and Monitors up to Eight Voltage
• Test Equipment
Rails
• Any System Requiring Sequencing of Multiple
• Rail Voltages Sampled Every 50 µ s With
Voltage Rails
3.2-mV Resolution
• Four Configurable Digital Outputs for
Power-On Reset and Other Functions
The UCD9080 power-supply sequencer controls the
• Configurable Rail-Enable Output Polarity
enable sequence of up to eight independent voltage
• Flexible Rail Sequencing: Timeline (ms),
rails and provides four general-purpose digital
Parent Rail Regulation Window, Parent Rail
outputs. The device operates from a 3.3-V supply,
Achieving Defined Threshold
provides 3.2-mV resolution of voltage rails, and
requires no external memory or clock. The UCD9080
• Under- and Overvoltage Thresholds: Settable
monitors the voltage rails independently at more than
Per-Rail
a 20-kHz rate and has a high degree of rail sequence
• Regulation Expiration Time: Settable Per-Rail
and rail error-response configurability. The
• Flexible Rail Shutdown: Parent Rail Shutdown
sequencing of rails can be based on time or on time
Can Shut Down Child Rails, Independent Rail
in conjunction with other rails achieving regulation or
Configuration a voltage threshold. In addition, each rail is monitored
for undervoltage and overvoltage glitches and
• Per-Rail Alarm Conditions, With Timestamp:
thresholds. Each rail the UCD9080 monitors can be
Under- and Overvoltage Glitch, Sustained
configured to shut down a user-defined set of other
Under- and/or Overvoltage, Rail Did Not Start
rails, and alarm conditions are monitored on a per-rail
• I
2
C Interface for Configuration and Monitoring
basis.
• Microsoft
®
Windows
®
GUI for Configuration
Figure 1 shows the UCD9080 power-supply
and Monitoring
sequencer in a typical application.
Figure 1. Typical Application Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 TMS320 is a trademark of Texas Instruments.
3 Microsoft, Windows are registered trademarks of Microsoft Corporation.
4 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
UCD9080
SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008 ...................................................................................................................................................
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com .
VALUE UNIT
Voltage applied from VCC to VSS – 0.3 to 4.1 V
Voltage applied to any pin
(2)
– 0.3 to V
CC
+ 0.3 V
Diode current at any device terminal ± 2 mA
T
stg
Storage temperature – 40 to 85 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS.
MIN NOM MAX UNIT
Supply voltage during operation 3 3.3 3.6
V
CC
V
Supply voltage during configuration changes 3 3.3 3.6
T
A
Operating free-air temperature range – 40 85 ° C
These specifications are over recommended ranges of supply voltage and operating free-air temperature, unless otherwise
noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
SUPPLY CURRENT
Supply current into V
CC
, excluding external
I
S
T
A
= 25 ° C 3 4 mA
current
I
C
Supply current during configuration 3.6 V 3 7 mA
STANDARD INPUTS (RST, TEST)
V
IL
Low-level input voltage V
CC
= 3 V V
SS
V
SS
+ 0.6 V
V
IH
High-level input voltage V
CC
= 3 V 0.8 V
CC
V
CC
V
SCHMITT TRIGGER INPUTS (SDA, SCL, EN1, EN2, EN3, EN4, EN5, EN6, EN7, EN8/ADDR1, ADDR2, ADDR3, ADDR4)
V
IT+
Positive-going input threshold voltage V
CC
= 3 V 1.5 1.9 V
V
IT –
Negative-going input threshold voltage V
CC
= 3 V 0.9 1.3 V
V
hys
Input-voltage hysteresis, (V
IT+
– V
IT –
) V
CC
= 3 V 0.5 1 V
I
lkg
High-impedance leakage current ± 50 nA
2 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s) :UCD9080
UCD9080
www.ti.com
................................................................................................................................................... SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS (continued)
These specifications are over recommended ranges of supply voltage and operating free-air temperature, unless otherwise
noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ANALOG INPUTS (MON1, MON2, MON3, MON4, MON5, MON6, MON7, MON8, ROSC)
V
CC
Analog supply voltage V
SS
= 0 V 3 3.6 V
Internal voltage reference 0 2.5
V
(R<1..8>)
Analog input voltage V
External voltage reference
0 V
CC
(V
CC
= 3.3 V used as reference)
Only one terminal can be selected at a time
C
I
(1)
Input capacitance 27 pF
(MON1 – MON8)
Input MUX ON resistance 0 V ≤ V
(MONx)
≤ VCC, V
CC
= 3 V 2000 Ω
R
I
(1)
I
lkg
High-impedance leakage current MON1 – MON8 ± 50 nA
REF2_5V = 1 for 2.5 V I
(VREF+)
≤
VREF+ Positive internal reference voltage output 2.35 2.5 2.65 V
I
(VREF+)
max, V
CC
= 3 V
REF2_5V = 1, I
(VREF+)
≤ 0.5 mA 3 V
VCC minimum voltage, positive built-in
V
CC
(min)
reference active
REF2_5V = 1, I
(VREF+)
≤ 1 mA 3 V
Internal reference (2.5 V) ± 6.8 ± 12 ± 17.4
V
(acc)
Accuracy of voltage sampling from rails mV
External reference (3.3 V/V
CC
) ± 0.2 ± 1.6 ± 6.8
Temperature coefficient of built-in I
(VREF+)
is a constant in the range of
± 100 ppm/ ° C
T
REF+
(1)
reference 0 mA ≤ I
(VREF+)
≤ 1 mA, VCC = 3 V
MISCELLANEOUS
t
retention
Retention of configuration parameters T
J
= 25 ° C 100 Years
POR, Brownout, Reset
(2) (3)
t
d(BOR)
2000 µ s
VCC
(start)
0.7 × V
(B_IT – )
V
V
(B_IT – )
VCC/dt ≤ 3 V/s 1.71 V
Brownout
V
hys(B_IT – )
70 130 180 mV
Pulse length needed at RST pin to accept
t
(reset)
2 µ s
reset internally, V
CC
= 3 V
DIGITAL OUTPUTS (EN8/GPO1, GPO2, GPO3, GPO4, EN1, EN2, EN3, EN4, EN5, EN6, EN7, SDA, SCL )
I
OH
(max) = – 1.5 mA,
(4)
V
CC
= 3 V V
CC
– 0.25 V
CC
V
OH
High-level output voltage V
I
OH
(max) = – 6 mA,
(5)
V
CC
= 3 V V
CC
– 0.6 V
CC
I
OH
(max)= – 1.5 mA,
(4)
V
CC
= 3 V V
SS
V
SS
+ 0.25
V
OL
Low-level output voltage V
I
OH
(max) = – 6 mA,
(5)
V
CC
= 3 V V
SS
V
SS
+ 0.6
I
lkg
High-impedance leakage current V
CC
= 3 V ± 50 nA
(1) Not production tested. Limits verified by design.
(2) The current consumption of the brownout module is already included in the I
CC
current-consumption data.
(3) During power up, device initialization starts subsequent to a period of t
d(BOR)
after V
CC
= V
(B_IT – )
+ V
hys(B_IT – )
.
(4) The maximum total current, I
OH
max and I
OL
max, for all outputs combined, should not exceed ± 12 mA to hold the maximum voltage drop
specified.
(5) The maximum total current, I
OH
max and I
OL
max, for all outputs combined, should not exceed ± 48 mA to hold the maximum voltage drop
specified.
The UCD9080 is compatible with 3.3-V IO ports of microcontrollers, TMS320™ DSP family as well as ASICs.
The UCD9080 is available in a plastic 32-pin QFN package (RHB).
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s) :UCD9080
DIGITAL OUTPUTS (Only One Output Loaded at a Time)
V − High-LevelOutputVoltage − V
OH
10−
3
I TypicalHigh-LevelOutputCurrent mA
OH
− −
V =3V
P1.0
CC
T =85 C
A
o
T =25 C
A
o
0 0.5 1 1.5 2 3.52.5
−30
0
−50
−20
−60
−40
V − Low-LevelOutputVoltage − V
OL
10
3
I TypicalLow-LevelOutputCurrent mA
OL
− −
V =3V
P1.0
CC
T =85 C
A
o
T =25 C
A
o
0 0.5 1 1.5 2 3.52.5
30
0
50
20
40
0
1
V
CC
V
(B_IT–)
V
hys(B_IT–)
V
CC(start)
t
d(BOR)
Setsignalfor
PORcircuitry
UCD9080
SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008 ...................................................................................................................................................
www.ti.com
TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs vs
LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
Figure 2. Figure 3.
Figure 4. POR/Brownout Reset (BOR) vs Supply Voltage
4 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s) :UCD9080
V =3V
TypicalConditions
CC
V
V
C
C(min)
-
t PulseWidth S
pw
- - m
t PulseWidth S
pw
- - m
t
pw
V
CC
V
CC(min)
3V
1ns
2
1
1.5
1000
0
0.5
0.001
1
1ns
V =3V
TypicalConditions
CC
V
V
CC(min)
-
t PulseWidth S
pw
- - m
t PulseWidth s
pw
- - m
t
pw
t t
fall
=
rise
t
fall
t
rise
V
CC
V
CC(min)
3V
2
1
1.5
1000
0
0.5
0.001
1
I
2
C TIMING
S
SDA
SCL
SPSr
t
r
t
SU;STO
t
BUF
t
HD;STA
t
SU;STA
t
r
t
HIGH
t
HD;DAT
t
SU;DAT
t
HD;STA
t
LOW
t
f
t
of
UCD9080
www.ti.com
................................................................................................................................................... SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008
Figure 5. V
CC(min)
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
Figure 6. V
CC(min)
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
The UCD9080 supports the same timing parameters as standard-mode I
2
C. See the following timing diagram
and timing parameters for more information.
Figure 7. Timing Diagram for I
2
C Interface
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s) :UCD9080
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