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UCD9248

www.ti.com

SLVSA33A –JANUARY 2010–REVISED AUGUST 2012

Digital PWM System Controller

FEATURES

APPLICATIONS

• Fully Configurable Multi-Output and Multi-

• Industrial/ATE

Phase Non-Isolated DC/DC PWM Controller

• Networking Equipment

• Controls Up to 4 Voltage Rails and Up to 8

• Telecommunications Equipment

Phases

• Servers

• Supports Switching Frequencies Up to 2MHz

• Storage Systems

with 250 ps Duty-Cycle Resolution

• FPGA, DSP and Memory Power

• Up To 1mV Closed Loop Resolution

• Hardware-Accelerated, 3-Pole/3-Zero

DESCRIPTION

Compensator with Non-Linear Gain for

The UCD9248 is a multi-rail, multi-phase

Improved Transient Performance

synchronous buck digital PWM controller designed for

non-isolated DC/DC power applications. This device

• Supports Multiple Soft-Start and Soft-Stop

integrates dedicated circuitry for DC/DC loop

Configurations Including Prebias Start-up

management with flash memory and a serial interface

• Supports Voltage Tracking, Margining and

to support configurability, monitoring and

Sequencing

management.

• Supports Current and Temperature Balancing

The UCD9248 was designed to provide a wide

for Multi-Phase Power Stages

variety of desirable features for non-isolated DC/DC

• Supports Phase Adding/Shedding for Multi-

converter applications while minimizing the total

Phase Power Stages

system component count by reducing external

circuits. The solution integrates multi-loop

• Sync In/Out Pins Align DPWM Clocks Between

management with sequencing, margining, tracking

Multiple UCD92xx Devices

and intelligent phase management to optimize for

• 12-Bit Digital Monitoring of Power Supply

total system efficiency. Additionally, loop

Parameters Including:

compensation and calibration are supported without

– Input/Output Current and Voltage

the need to add external components.

– Temperature at Each Power Stage

To facilitate configuring the device, the Texas

• Multiple Levels of Over-current Fault

Instruments Fusion Digital Power™ Designer is

provided. This PC based Graphical User Interface

Protection:

offers an intuitive interface to the device. This tool

– External Current Fault Inputs

allows the design engineer to configure the system

– Analog Comparators Monitor Current

operating parameters for the application, store the

Sense Voltage

configuration to on-chip non-volatile memory and

observe both frequency domain and time domain

– Current Continually Digitally Monitored

simulations for each of the power stage outputs.

• Over- and Under-voltage Fault Protection

TI has also developed multiple complementary power

• Over-temperature Fault Protection

stage solutions – from discrete drivers in the UCD7k

• Enhanced Nonvolatile Memory with Error

family to fully tested power train modules in the PTD

Correction Code (ECC)

family. These solutions have been developed to

• Device Operates From a Single Supply with an

complement the UCD9k family of system power

Internal Regulator Controller That Allows

controllers.

Operation Over a Wide Supply Voltage Range

• Supported by Fusion Digital Power™

Designer, a Full Featured PC Based Design

Tool to Simulate, Configure, and Monitor

Power Supply Performance

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

UCD9248

SLVSA33A –JANUARY 2010–REVISED AUGUST 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

OPERATING TEMPERATURE ORDERABLE PART PIN COUNT SUPPLY PACKAGE TOP SIDE

RANGE, T

NUMBER MARKING

UCD9248PFCR 80-pin Reel of 1000 QFP UCD9248

–40°C to 125°C

UCD9248PFC 80-pin Tray of 119 QFP UCD9248

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

VALUE UNIT

Voltage applied at V

33D

to DGND –0.3 to 3.8 V

Voltage applied at V

33A

to AGND –0.3 to 3.8 V

Voltage applied to any pin

(2)

–0.3 to 3.8 V

Storage temperature (T

STG

) –40 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to GND.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

V Supply voltage during operation, V

33D

, V

33DIO

, V

33A

3 3.3 3.6 V

Operating free-air temperature range

(1)

–40 125 °C

Junction temperature

(1)

125 °C

(1) When operating, the UCD9248’s typical power consumption causes a 15°C temperature rise from ambient.

ELECTRICAL CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

V33A

33A

= 3.3 V 8 15

V33DIO

33DIO

= 3.3 V 2 10

Supply current mA

V33D

33D

= 3.3 V 40 45

33D

= 3.3 V storing configuration parameters

V33D

50 55

in flash memory

INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS

3.3-V linear regulator Emitter of NPN transistor 3.25 3.3 3.6

33FB

3.3-V linear regulator feedback 4 4.6

V33FB

Series pass base drive V

VIN

= 12 V 10 mA

Beta Series NPN pass device 40

EXTERNALLY SUPPLIED 3.3 V POWER

33D

Digital 3.3-V power T

= 25° C 3.0 3.6 V

33A

Analog 3.3-V power T

= 25°C 3.0 3.6 V

UCD9248

www.ti.com

SLVSA33A –JANUARY 2010–REVISED AUGUST 2012

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ERROR AMPLIFIER INPUTS EAPn, EANn

Common mode voltage each pin –0.15 1.848 V

ERROR

Internal error voltage range AFE_GAIN field of CLA_GAINS = 0

(1)

–256 248 mV

EAP-EAN Error voltage digital resolution AFE_GAIN field of CLA_GAINS= 3 1 mV

Input Impedance Ground reference 0.5 1.5 3 MΩ

OFFSET

Input offset current 1 kΩ source impedence –5 5 µA

Vref 10-bit DAC

ref

Reference voltage setpoint 0 1.6 V

refres

Reference voltage resolution 1.56 mV

ANALOG INPUTS CS-1A, CS-1B, CS-2A, CS-2B, CS-3A, CS-3B, CS-4A, CS-4B, Vin/I

, TEMP, ADDR-0, ADDR-1, Vtrack, ADCref

ADDR_OPEN

Voltage indicating open pin ADDR-0, ADDR-1 open 2.37 V

ADDR_SHORT

Voltage indicating shorted pin ADDR-0, ADDR-1 short to ground 0.36 V

Inputs: Vin/I

, Vtrack, Temp, CS-1A, CS-1B,

ADC_RANGE

Measurement range for voltage monitoring 0 2.5 V

CS-2A, CS-2B CS-3A, CS-3B, CS-4A, CS-4B

Over-current comparator threshold voltage

OC_THRS

Inputs: CS-1A, CS-2A, CS-3A, CS-4A 0.032 2 V

range

(2)

Over-current comparator threshold voltage

OC_RES

Inputs: CS-1A, CS-2A, CS-3A, CS-4A 31.25 mV

range

ADCref External reference input 1.8 V

33A

Temp

internal

Int. temperature sense accuracy Over range from 0°C to 125°C –5 5 °C

INL ADC integral nonlinearity –2.5 2.5 mV

lkg

Input leakage current 3V applied to pin 100 nA

Input impedance Ground reference 8 MΩ

Current Sense Input capacitance 10 pF

DIGITAL INPUTS/OUTPUTS

Dgnd

Low-level output voltage I

= 6 mA

(3)

, V

33DIO

= 3 V V

+0.25

33DIO

High-level output voltage I

= -6 mA

(4)

, V

33DIO

= 3 V V

–0.6V

High-level input voltage V

33DIO

= 3V 2.1 3.6 V

Low-level input voltage V

33DIO

= 3.5 V 1.4 V

SYSTEM PERFORMANCE

RESET

Voltage where device comes out of reset V

33D

Pin 2.3 2.4 V

RESET

Pulse width needed for reset nRESET pin 2 µs

ref

commanded to be 1V, at 25°C,

RefAcc

Setpoint reference accuracy –10 10 mV

AFEgain = 4, 1V input to EAP/N measured at

output of the EADC

(5)

Setpoint reference accuracy over temperature –40°C to 125°C –20 20 mV

DiffOffset

Differential offset between gain settings AFEgain = 4 compared to AFEgain = 1, 2, or 8 –4 4 mV

240 + 1

Delay

Digital compensator delay 240 switching ns

cycle

Switching frequency 15.260 2000 kHz

Duty Max and Min duty cycle 0% 100%

Slew Minimum V

slew rate during power on V

slew rate between 2.3V and 2.9V 0.25 V/ms

retention

Retention of configuration parameters T

= 25°C 100 Years

Write_Cycles Number of nonvolatile erase/write cycles T

= 25°C 20 K cycles

(1) See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command.

(2) Can be disabled by setting to '0'

(3) The maximum I

, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.

(4) The maximum I

, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.

(5) With default device calibration. PMBus calibration can be used to improve the regulation tolerance

UCD9248

SLVSA33A –JANUARY 2010–REVISED AUGUST 2012

www.ti.com

ADC MONITORING INTERVALS AND RESPONSE TIMES

The ADC operates in a continuous conversion sequence that measures each rail's output voltage, each power

stage's output current, plus four other variables (external temperature, Internal temperature, input voltage and

current, and tracking input voltage). The length of the sequence is determined by the number of output rails

(NumRails) and total output power stages (NumPhases) configured for use. The time to complete the monitoring

sampling sequence is give by the formula:

ADC_SEQ

= t

ADC

× (NumRAILS + NumPHASE + 4)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC

ADC single-sample time 3.84 µs

Min = 1 Rail + 1 Phase + 4 = 6 samples Max = 4

ADC_SEQ

ADC sequencer interval 23.04 61.44 µs

Rails + 8 Phases + 4 = 16 samples

The most recent ADC conversion results are periodically converted into the proper measurement units (volts,

amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The

monitoring operates asynchronously to the ADC, at intervals shown in the table below.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Vout

Output voltage monitoring interval 200 µs

Iout

Output current monitoring interval 200 × NRails µs

Vin

Input voltage monitoring interval 2 ms

Iin

Input current monitoring interval 2 ms

TEMP

Temperature monitoring interval 100 ms

Ibal

Output current balancing interval 2 ms

Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response

time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC

sequence interval. Once a fault condition is detected, some additional time is required to determine the correct

action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following

table lists the worse-case fault response times.

PARAMETER TEST CONDITIONS MAX TIME UNIT

Over-/under-voltage fault response time during Normal regulation, no PMBus activity, 8

300 µs

normal operation stages enabled

Over-/under-voltage fault response time, during

OVF

, t

UVF

During data logging to nonvolatile memory

(1)

800 µs

data logging

Over-/under-voltage fault response time, when

During tracking and soft-start ramp. 400 µs

tracking or sequencing enable

Over-/under-current fault response time during Normal regulation, no PMBus activity, 8

100 + (600 × NRails) µs

normal operation stages enabled 75% to 125% current step

Over-/under-current fault response time, during During data logging to nonvolatile memory

OCF

, t

UCF

600 + (600 × NRails) µs

data logging 75% to 125% current step

Over-/under-current fault response time, when During tracking and soft start ramp 75% to

300 + (600 × NRails) µs

tracking or sequencing enable 125% current step

Temperature rise of 10°C/sec,

OTF

Over-temperature fault response time 2.5 S

OT threshold = 100°C

(1) During a STORE_DEFAULT_ALL command, which stores the entire configuration to nonvolatile memory, the fault detection latency can

be up to 10 ms.

UCD9248

www.ti.com

SLVSA33A –JANUARY 2010–REVISED AUGUST 2012

HARDWARE FAULT DETECTION LATENCY

The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.

PARAMETER TEST CONDITIONS MAX UNIT

FAULT

Time to disable DPWM output based on corresponding 15 + 3 ×

High level on FAULT pin µs

active FLTpin NumPhases

Time to disable the first DPWM output based on Step change in CS voltage from 0V to Switch

internal analog comparator fault 2.5V Cycles

CLF

Time to disable all remaining DPWM and SRE outputs

Step change in CS voltage from 0V to 10 + 3 ×

configured for the voltage rail after an internal analog µs

2.5V NumPhases

comparator fault

PMBUS/SMBUS/I2C

The timing characteristics and timing diagram for the communications interface that supports I

C, SMBus and

PMBus are shown below.

C/SMBus/PMBus TIMING CHARACTERISTICS

= –40°C to 125°C, 3V < V33 < 3.6V, typical values at T

= 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SMB

SMBus/PMBus operating frequency Slave mode; SMBC 50% duty cycle 10 1000 kHz

I2C

I2C operating frequency Slave mode; SCL 50% duty cycle 10 1000 kHz

(BUF)

Bus free time between start and stop 4.7 µs

(HD:STA)

Hold time after (repeated) start 0.26 µs

(SU:STA)

Repeated start setup time 0.26 µs

(SU:STO)

Stop setup time 0.26 µs

(HD:DAT)

Data hold time Receive mode 0 ns

(SU:DAT)

Data setup time 50 ns

(TIMEOUT)

Error signal/detect See

(1)

35 ms

(LOW)

Clock low period 0.5 µs

(HIGH)

Clock high period See

(2)

0.26 50 µs

(LOW:SEXT)

Cumulative clock low slave extend time See

(3)

25 ms

FALL

Clock/data fall time See

(4)

120 ns

RISE

Clock/data rise time See

(5)

120 ns

(1) The UCD9248 times out when any clock low exceeds t(TIMEOUT).

(2) t

(HIGH)

, max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9248 that is

in progress.

(3) t

(LOW:SEXT)

is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(4) Rise time t

RISE

= V

ILMAX

– 0.15) to (V

IHMIN

+ 0.15)

(5) Fall time t

FALL

= 0.9 V

to (V

ILMAX

– 0.15)

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