module multi(CLK,A,B,a,b,c,d,e,f,g,START,q0,q1,q2,q3);
reg BO0,TIME4,LCE,PLE,SCE,PEND,CP;
parameter r=2;
reg [1:0] current=2'b00,next;
parameter S0=2'b00,S1=2'b01,S2=2'b10;
input CLK,START;
input [(r-1):0] A,B;
output reg a,b,c,d,e,f,g,q0,q1,q2,q3;
reg [3:0] z;
reg [(2*r-1):0] P,p;
reg [(r-1):0] a1,b1,a0,b0;
reg cout;
reg [15:0] m;
always @ (posedge CLK)
begin
if(m<49999) m<=m+1;
else m<=16'b0000000000000000;
end
always @ (m[15])
begin CP=m[15];
end
always @ (posedge CP)
begin
current<=next;
end
always @ (START or BO0 or TIME4 or current)
begin
case(current)
S0:begin
if(START==0) begin next=S0;LCE=0;PLE=0;SCE=0;PEND=1; end
else begin next=S1;LCE=1;PLE=0;SCE=0;PEND=0; end
end
S1:begin
if(BO0==0) begin next=S2;LCE=0;PLE=0;SCE=1;PEND=0; end
else begin next=S2;LCE=0;PLE=1;SCE=1;PEND=0; end
end
S2:begin
if(BO0==1&&TIME4==0) begin next=S2;LCE=0;PLE=1;SCE=1;PEND=0; end
else if(BO0==0&&TIME4==0) begin next=S2;LCE=0;PLE=0;SCE=1;PEND=0; end
else if(TIME4==1) begin next=S0;LCE=0;PLE=0;SCE=0;PEND=1; end
end
endcase
end
reg [1:0] t;
reg [(r-1):0] h;
always @ (posedge CP)
begin
if(LCE) begin
a1<=A;b1<=B;p<=4'b0000;a0<=A;b0<=B;BO0<=b1[0];t<=0;
end
if(PLE) begin p[(2*r-1):(r-1)]<=a1+p[(2*r-1):(r)]; end
if(SCE) begin p<=p>>1;b1<=b1>>1; BO0<=b1[0];
if(t<(r-1)) begin t<=t+1;TIME4=1'b0;end
else begin t<=0; TIME4=1'b1; end
end
if(PEND) begin P<=p; end
