DS90CR483A, DS90CR484A
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SNLS291A –APRIL 2008–REVISED APRIL 2013
DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz
Check for Samples: DS90CR483A, DS90CR484A
The multiplexing of data lines provides a substantial
1
FEATURES
cable reduction. Long distance parallel single-ended
2
• Up to 5.38 Gbits/sec Bandwidth
buses typically require a ground wire per active signal
• 33 MHz to 112 MHz Input Clock Support
(and have very limited noise rejection capability).
Thus, for a 48-bit wide data and one clock, up to 98
• LVDS SER/DES Reduces Cable and Connector
conductors are required. With this Channel Link
Size
chipset as few as 19 conductors (8 data pairs, 1 clock
• Pre-emphasis Reduces Cable Loading Effects
pair and a minimum of one ground) are needed. This
• DC Balance Data Transmission Provided by
provides an 80% reduction in cable width, which
Transmitter Reduces ISI Distortion
provides a system cost savings, reduces connector
physical size and cost, and reduces shielding
• Cable Deskew of +/−1 LVDS Data Bit Time (up
requirements due to the cables' smaller form factor.
to 80 MHz Clock Rate)
The 48 CMOS/TTL inputs can support a variety of
• 5V Tolerant TxIN and Control Input Pins
signal combinations. For example, 6 8-bit words or 5
• Flow Through Pinout for Easy PCB Design
9-bit (byte + parity) and 3 controls.
• +3.3V Supply Voltage
The DS90CR483A/DS90CR484A chipset is improved
• Transmitter Rejects Cycle-to-Cycle Jitter
over prior generations of Channel Link devices and
• Conforms to ANSI/TIA/EIA-644-1995 LVDS
offers higher bandwidth support and longer cable
Standard
drive with three areas of enhancement. To increase
bandwidth, the maximum clock rate is increased to
• Both Devices are Available in 100 Lead TQFP
112 MHz and 8 serialized LVDS outputs are
Package
provided. Cable drive is enhanced with a user
selectable pre-emphasis feature that provides
DESCRIPTION
additional output current during transitions to
The DS90CR483A transmitter converts 48 bits of
counteract cable loading effects. Optional DC
CMOS/TTL data into eight LVDS (Low Voltage
balancing on a cycle-to-cycle basis, is also provided
Differential Signaling) data streams. A phase-locked
to reduce ISI (Inter-Symbol Interference). With pre-
transmit clock is transmitted in parallel with the data
emphasis and DC balancing, a low distortion eye-
streams over a ninth LVDS link. Every cycle of the
pattern is provided at the receiver end of the cable. A
transmit clock 48 bits of input data are sampled and
cable deskew capability has been added to deskew
transmitted. The DS90CR484A receiver converts the
long cables of pair-to-pair skew of up to +/−1 LVDS
LVDS data streams back into 48 bits of CMOS/TTL
data bit time (up to 80 MHz Clock Rate). These three
data. At a transmit clock frequency of 112MHz, 48
enhancements allow cables 5+ meters in length to be
bits of TTL data are transmitted at a rate of 672Mbps
driven.
per LVDS data channel. Using a 112MHz clock, the
The chipset is an ideal means to solve EMI and cable
data throughput is 5.38Gbit/s (672Mbytes/s).
size problems associated with wide, high speed TTL
interfaces.
For more details, please refer to the Applications
Information section of this datasheet.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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