【免费】TI-PCA9557.pdf资源-CSDN文库

RGVPACKAGE

(TOP VIEW)

5

6

7

8

9

10

11

12

13

14

1516

1

2

3

4

A1

A2

P0

A0

P4

P7

SCL

SDA

V

CC

RESET

P6

P1

GND

P3

P2

P5

D,DB,DGV,ORPWPACKAGE

(TOP VIEW)

5

6

7

8 9

10

11

12

13

14

15

16

1

2

3

4

P1

A1

A2

P0

A0

GND

SCL

SDA

V

CC

P4

P7

RESET

P3

P6

P2

P5

RGYPACKAGE

(TOP VIEW)

5

6

7 10

11

12

13

14

15

16

1

2

3

4

SDA

SCL

V

CC

A1

A2

P0

A0

P1

8 9

GND

P2

P4

P7

RESET

P6

P3

P5

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

PCA9557

SCPS133J –DECEMBER 2005–REVISED JUNE 2014

PCA9557 Remote 8-Bit I

2

C and SMBus Low-Power I/O Expander With Reset and

Configuration Registers

1 Features 2 Description

This 8-bit I/O expander for the two-line bidirectional

1

• Low Standby Current Consumption of 1 μA Max

bus (I

2

C) is designed for 2.3-V to 5.5-V V

CC

• I

2

C to Parallel Port Expander

operation. The device provides general-purpose

• Operating Power-Supply Voltage Range of 2.3 V

remote I/O expansion for most microcontroller

to 5.5 V

families via the I

2

C interface [serial clock (SCL) and

serial data (SDA)].

• 5-V Tolerant I/O Ports

• 400-kHz Fast I

2

C Bus

The PCA9557 consists of one 8-bit configuration

(input or output selection), input port, output port, and

• Three Hardware Address Pins Allow for Use of up

polarity inversion (active-high) registers. At power on,

to Eight Devices on I

2

C/SMBus

the I/Os are configured as inputs. However, the

• Lower-Voltage Higher-Performance Migration

system master can enable the I/Os as either inputs or

Path for PCA9556

outputs by writing to the I/O configuration bits. The

data for each input or output is kept in the

• Input/Output Configuration Register

corresponding input or output register. The polarity of

• Polarity Inversion Register

the input port register can be inverted with the polarity

• Active-Low Reset Input

inversion register. All registers can be read by the

• Internal Power-On Reset

system master.

• High-Impedance Open Drain on P0

The device outputs (latched) have high-current drive

• Power Up With All Channels Configured as Inputs

capability for directly driving LEDs. The device has

low current consumption.

• No Glitch on Power Up

• Noise Filter on SCL/SDA Inputs

Device Information

(1)

• Latched Outputs With High Current Drive

PART NUMBEr PACKAGE BODY SIZE (NOM)

Maximum Capability for Directly Driving LEDs

SSOP (16) 6.20 mm × 5.30 mm

PCA9557

• Latch-Up Performance Exceeds 100 mA Per

VQFN (16) 4.00 mm × 4.00 mm

JESD 78, Class II

(1) For all available packages, see the orderable addendum at

• ESD Protection Exceeds JESD 22

the end of the datasheet.

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

PCA9557

SCPS133J –DECEMBER 2005–REVISED JUNE 2014

www.ti.com

Table of Contents

1 Features.................................................................. 1 8 Detailed Description............................................ 12

8.1 Functional Block Diagram ....................................... 12

2 Description ............................................................. 1

8.2 Device Functional Modes........................................ 14

3 Revision History..................................................... 2

8.3 Programming........................................................... 15

4 Description (Continued)........................................ 3

8.4 Bus Transactions .................................................... 19

5 Pin Configuration and Functions......................... 3

9 Application And Implementation........................ 21

6 Specifications......................................................... 4

9.1 Application Information............................................ 21

6.1 Absolute Maximum Ratings ...................................... 4

9.2 Typical Application ................................................. 21

6.2 Handling Ratings ...................................................... 4

10 Power Supply Recommendations ..................... 22

6.3 Recommended Operating Conditions....................... 4

10.1 Power-On Reset Errata......................................... 22

6.4 Electrical Characteristics........................................... 5

11 Device and Documentation Support ................. 23

6.5 I

2

C Interface Timing Requirements........................... 6

11.1 Trademarks........................................................... 23

6.6 Reset Timing Requirements ..................................... 6

11.2 Electrostatic Discharge Caution............................ 23

6.7 Switching Characteristics.......................................... 6

11.3 Glossary................................................................ 23

6.8 Typical Characteristics.............................................. 7

12 Mechanical, Packaging, and Orderable

7 Parameter Measurement Information .................. 9

Information ........................................................... 23

3 Revision History

Changes from Revision I (June 2008) to Revision J Page

• Added RESET Errata section............................................................................................................................................... 14

• Added Power-On Reset Errata section. ............................................................................................................................... 22

Product Folder Links: PCA9557

RGVPACKAGE

(TOP VIEW)

5

6

7

8

9

10

11

12

13

14

1516

1

2

3

4

A1

A2

P0

A0

P4

P7

SCL

SDA

V

CC

RESET

P6

P1

GND

P3

P2

P5

D,DB,DGV,ORPWPACKAGE

(TOP VIEW)

5

6

7

8 9

10

11

12

13

14

15

16

1

2

3

4

P1

A1

A2

P0

A0

GND

SCL

SDA

V

CC

P4

P7

RESET

P3

P6

P2

P5

RGYPACKAGE

(TOP VIEW)

5

6

7 10

11

12

13

14

15

16

1

2

3

4

SDA

SCL

V

CC

A1

A2

P0

A0

P1

8 9

GND

P2

P4

P7

RESET

P6

P3

P5

PCA9557

www.ti.com

SCPS133J –DECEMBER 2005–REVISED JUNE 2014

4 Description (Continued)

The system master can reset the PCA9557 in the event of a timeout or other improper operation by asserting a

low in the active-low reset (RESET) input. The power-on reset puts the registers in their default state and

initializes the I

2

C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without

depowering the part.

Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I

2

C address, allowing up to eight

devices to share the same I

2

C bus or SMBus.

5 Pin Configuration and Functions

Pin Functions

QFN (RGY)

SOIC (D),

DESCRIPTION

SSOP (DB),

NAME QFN (RGV)

TSSOP (PW),

AND

TVSOP (DGV)

SCL 1 15 Serial clock bus. Connect to V

CC

through a pullup resistor.

SDA 2 16 Serial data bus. Connect to V

CC

through a pullup resistor.

A0 3 1 Address input. Connect directly to V

CC

or ground.

A1 4 2 Address input. Connect directly to V

CC

or ground.

A2 5 3 Address input. Connect directly to V

CC

or ground.

P-port input/output. High impedance open-drain design structure. Connect to

P0 6 4

V

CC

through a pullup resistor.

P1 7 5 P-port input/output. Push-pull design structure.

GND 8 6 Ground

P2 9 7 P-port input/output. Push-pull design structure.

P3 10 8 P-port input/output. Push-pull design structure.

P4 11 9 P-port input/output. Push-pull design structure.

P5 12 10 P-port input/output. Push-pull design structure.

P6 13 11 P-port input/output. Push-pull design structure.

P7 14 12 P-port input/output. Push-pull design structure.

Active-low reset input. Connect to V

CC

through a pullup resistor if no active

RESET 15 13

connection is used.

V

CC

16 14 Supply voltage

Product Folder Links: PCA9557

PCA9557

SCPS133J –DECEMBER 2005–REVISED JUNE 2014

www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

V

CC

Supply voltage range –0.5 6 V

V

I

Input voltage range

(2)

–0.5 6 V

V

O

Output voltage range

(2)

–0.5 6 V

I

IK

Input clamp current V

I

< 0 –20 mA

I

OK

Output clamp current V

O

< 0 –20 mA

I

IOK

Input/output clamp current V

O

< 0 or V

O

> V

CC

–20 μA

I

OL

Continuous output low current V

O

= 0 to V

CC

50 mA

I

OH

Continuous output high current V

O

= 0 to V

CC

–50 mA

Continuous current through GND –250

I

CC

mA

Continuous current through V

CC

160

D package 73

DB package 82

DGV package 120

θ

JA

Package thermal impedance

(3)

°C/W

PW package 108

RGV package 51

RGY package 47

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

6.2 Handling Ratings

MIN MAX UNIT

T

stg

Storage temperature range –65 150 °C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

0 2000

pins

(1)

V

(ESD)

Electrostatic discharge V

Charged device model (CDM), per JEDEC specification

0 1000

JESD22-C101, all pins

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT

V

CC

Supply voltage 2.3 5.5 V

SCL, SDA 0.7 × V

CC

5.5

V

IH

High-level input voltage V

A2–A0, P7–P0, RESET 2 5.5

SCL, SDA –0.5 0.3 × V

CC

V

IL

Low-level input voltage V

A2–A0, P7–P0, RESET –0.5 0.8

I

OH

High-level output current P7–P1 –10 mA

I

OL

Low-level output current P7–P0 25 mA

T

A

Operating free-air temperature –40 85 °C

Product Folder Links: PCA9557

剩余39页未读，继续阅读

TI-PCA9557.pdf

TI-CD74HC4543.pdf

TI-TL16C550C.pdf

TI-SN75LVPE801.pdf

TI-UCD3040.pdf

TI-TPS658640.pdf

TI-PCA9518.pdf

TI-PCA9306.pdf

TI-PCA9555.pdf

TI-PCA9538.pdf

TI-TMUX1309.pdf

TI-LMH1226.pdf

TI-CSD96370Q5M.pdf

TI-LMH34400.pdf

TI-TPS1663.pdf

TI-PCA9539.pdf

TI-PCA9554.pdf

TI-PCA9543A.pdf

TI-PCA9306-Q1.pdf

TI-PCA9548A.pdf

TI-LMH1981.pdf

TI-TPS51116.pdf

TI-TPS55289.pdf

TI-TPS23861.pdf

TI-AFE5812.pdf

TI-PCA9544A.pdf

TI-PCA9545A.pdf

TI-PCA9546A.pdf

TI-PCA9515B.pdf

TI-PCA9515A.pdf

最新资源