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TI-THS7353.pdf
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TI-THS7353.pdf
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In A
ADC/
Video
Decoder
3.3V
3.3V
LPF
AC
Sync
TIP
Clamp
DC
+
-
X1
DC+
250mV
MUTE
Bypass
2:1
1kW
250 W
AC -
BIAS
InB
InputB
Input A
I2C-
SDA
I2C-
SCL
9/16/
35MHz
Out
Gain
Adjust
0.1 Fm
0.1 Fm
0.1 Fm
75 W
75 W
1of3Channels
THS7353
www.ti.com
SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012
3-Channel Low Power Video Buffer with I
2
C Control, Selectable Filters, External Gain
Control, 2:1 Input MUX, and Selectable Input Modes
Check for Samples: THS7353
1
FEATURES
APPLICATIONS
234
• 3-Video Buffers for CVBS, S-Video, SD/ED/HD
• HDTV Video Buffering
Y'P'
B
P'
R
, and G'B'R' (R'G'B') Video
• PVR/DVDR Video Buffering
• I
2
C™ Control of All Functions
• Projector Video Buffering
• Integrated Low-Pass Filters
• USB/Portable Low Power Video Buffering
– 5
th
Order Butterworth Characteristics
DESCRIPTION
– Selectable Corner Frequencies of 9-MHz,
Fabricated using the new complimentary silicon-
16-MHz, 35-MHz, and Bypass (150-MHz)
germanium (SiGe) BiCom-III process, the THS7353 is
• Selectable Input Bias Modes
a low-power, single-supply 2.7-V to 5-V, 3-channel
– AC-Coupled with Sync-Tip Clamp
integrated video buffer. It incorporates a selectable
5
th
order Butterworth anti-aliasing / DAC
– AC-Coupled with Bias
reconstruction filter to eliminate data converter
– DC-Coupled with 250-mV Input Shift
images. The 9-MHz is a perfect choice for SDTV
– DC-Coupled
video including composite, S-Video™, and 480i/576i
• 2:1 Input MUX Allows Multiple Input Sources
Y'P'
B
P'
R
or G'B'R' (R'G'B') video. The 16-MHz filter is
ideal for EDTV 480p/576p Y'P'
B
P'
R
, G'B'R', and VGA
• External Gain Control Range From
signals. The 35-MHz filter is useful for HDTV
0 dB to 14 dB
720p/1080i Y'P'
B
P'
R
, G'B'R', and SVGA/XGA signals.
• 2.7-V to 5-V Single Supply Operation
For 1080p or SXGA/UXGA signals, the filter can be
• Low 16.2-mA (3.3 V) Total Quiescent Current
bypassed allowing a 150-MHz bandwidth, 300-V/μs
amplifier to buffer the signal.
• Disable (< 1 μA) and Mute Control Functions
Each channel of the THS7353 is individually I
2
C
• Rail-to-Rail Output:
configurable for all functions which makes it flexible
– Allows AC or DC Output Coupling
for any application. Its rail-to-rail output stage allows
• Low Differential Gain/Phase of 0.15%/0.3°
for both ac and dc coupling applications. The
externally controlled gain adjust pin allows for fine
tuning of the gain such as line driving, compensating
for cable losses, or Sin-X/X compensation.
Figure 1. 3.3 V Single-Supply AC-Input/AC-Video Output System w/SAG Correction
(1 of 3 Channels Shown)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2I
2
C is a trademark of NXP Semiconductors.
3S-Video is a trademark of of its respective owner.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
![](https://csdnimg.cn/release/download_crawler_static/87239992/bg2.jpg)
THS7353
SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
As part of the THS7353 flexibility, the 2:1 MUX input can be selected for ac or dc coupled inputs. The ac coupled
modes include a sync-tip clamp option for CVBS/Y'/G'B'R' with sync or a fixed bias for the C'/P'
B
/P'
R
channels.
The dc input options include a dc input or a dc + 250-mV input offset shift to allow for a full sync dynamic range
at the output with 0-V input.
The THS7353 is the perfect choice for all video buffer applications. The 16.2-mA total quiescent current (54 mW
total power) makes it an excellent choice for USB powered or portable video applications. While fully disabled,
the THS7353 consumes less than 1 μA.
PACKAGING/ORDERING INFORMATION
(1)
TRANSPORT MEDIA,
PACKAGED DEVICES PACKAGE TYPE
QUANTITY
THS7353PW Rails, 70
TSSOP-20
THS7353PWR Tape and reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range (unless otherwise noted).
UNIT
V
SS
Supply voltage, V
S+
to GND 5.5 V
V
I
Input voltage –0.4 V to V
S+
I
O
Output current ±125 mA
Continuous power dissipation See Dissipation Ratings Table
T
J
Maximum junction temperature, any condition
(2)
150°C
T
J
Maximum junction temperature, continuous operation, long term reliability
(3)
125°C
T
stg
Storage temperature range –65°C to 150°C
HBM 1500 V
ESD ratings CDM 2000 V
MM 100 V
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
(2) The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
(3) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
DISSIPATION RATINGS
POWER RATING
(1)
θ
JC
θ
JA
(T
J
= 125°C)
PACKAGE
(°C/W) (°C/W)
T
A
= 25°C T
A
= 85°C
TSSOP – 20 (PW) 32.3 83
(2)
1.2 W 0.48 W
(1) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase and
long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and reliability.
(2) This data was taken with the JEDEC High-K test PCB. For the JEDEC low-K test PCB, the θ
JA
is 125.8°C.
2 Copyright © 2005–2012, Texas Instruments Incorporated
![](https://csdnimg.cn/release/download_crawler_static/87239992/bg3.jpg)
THS7353
www.ti.com
SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
V
SS
Supply voltage, V
S+
2.7 5 V
T
A
Ambient temperature –40 85 °C
ELECTRICAL CHARACTERISTICS, V
S+
= 3.3 V
R
L
= 150 Ω to GND, Filter Select = 9 MHz, Input Bias = dc, Gain Adjust pin shorted to the output pin (unless otherwise
noted).
TYP OVERTEMPERATURE
PARAMETER TEST CONDITIONS
–40°C to
25°C 25°C 0°C to 70°C UNITS MIN/MAX
85°C
AC PERFORMANCE
Filter Select = 9 MHz
(1)
9 7.6/10.4 7.4/10.6 7.3/10.7 MHz Min/Max
Filter Select = 16 MHz
(1)
16 13.4/18.6 13.1/18.9 13/19 MHz Min/Max
Small-signal bandwidth
(–3 dB) V
O
– 0.2 V
PP
Filter Select = 35 MHz
(1)
35 26.9/40.6 26.6/40.9 26.5/41 MHz Min/Max
Filter Select = Bypass 150 MHz
Filter Select = 9 MHz 9 MHz
Filter Select = 16 MHz 16 MHz
Large-signal bandwidth
(–3 dB) V
O
– 1 V
PP
Filter Select = 35 MHz 35 MHz
Filter Select = Bypass 100 MHz
Slew rate Filter Select = Bypass: 2 V
PP
300 V/μs
Filter Select = 9 MHz 53.5 ns
Filter Select = 16 MHz 31 ns
Group delay at 100 kHz
Filter Select = 35 MHz 17.2 ns
Filter Select = Bypass 3.25 ns
Filter Select = 9 MHz: at 5.1 MHz 10.3 ns
Group delay variation with
Filter Select = 16 MHz: at 11 MHz 7.5 ns
respect to 100 kHz
Filter Select = 35 MHz: at 27 MHz 4.7 ns
Group delay matching All filters: channel-to-channel 0.5 ns
Filter Select = 9 MHz: at 5.75 MHz 0.25 -0.3/1.2 -0.5/1.4 -0.6/1.5 dB Min/Max
Filter Select = 9 MHz: at 27 MHz 43 33 32 31 dB Min
Filter Select = 16 MHz: at 11 MHz 0.35 -0.4/1.2 -0.6/1.4 -0.7/1.5 dB Min/Max
Attenuation with respect to
100 kHz
Filter Select = 16 MHz: at 54 MHz 47 35 34 33 dB Min
Filter Select = 35 MHz: at 27 MHz 0.75 -0.5/3.2 -0.6/3.4 -0.7/3.5 dB Min/Max
Filter Select = 35 MHz: at 74 MHz 29 13 12 11 dB Min
Mute feed thru Filter Select = Bypass: at 30 MHz -73 dB
Differential gain Filter Select = 9 MHz: NTSC/PAL 0.15%/0.22%
Differential phase Filter Select = 9 MHz: NTSC/PAL 0.3°/0.36°
Filter Select = 9 MHz –59 dB
Filter Select = 16 MHz –58 dB
Total harmonic distortion
f = 1 MHz, 1 V
PP
Filter Select = 35 MHz –55 dB
Filter Select = Bypass –59 dB
Filter Select = 9 MHz, 480i source 83 dB
Signal to noise ratio (unified
Filter Select = 16 MHz, 480p source 81 dB
weighting per CCIR 576-2
Filter Select = 35 MHz, 720p source 78 dB
recommendation)
Filter Select = Bypass
(2)
, 720p source 66 dB
Filter Select = 9 MHz: at 1 MHz –70 dB
Filter Select = 16 MHz: at 1 MHz –73 dB
Channel-to-Channel
Crosstalk (V
O
= 1 V
PP
)
Filter Select = 35 MHz: at 1 MHz –78 dB
Filter Select = Bypass: at 1 MHz –84 dB
(1) The Min/Max values listed are specified by design only.
(2) Bandwidth up to 100-MHz, No Weighting, Tilt Null
Copyright © 2005–2012, Texas Instruments Incorporated 3
![](https://csdnimg.cn/release/download_crawler_static/87239992/bg4.jpg)
THS7353
SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012
www.ti.com
ELECTRICAL CHARACTERISTICS, V
S+
= 3.3 V (continued)
R
L
= 150 Ω to GND, Filter Select = 9 MHz, Input Bias = dc, Gain Adjust pin shorted to the output pin (unless otherwise
noted).
TYP OVERTEMPERATURE
PARAMETER TEST CONDITIONS
–40°C to
25°C 25°C 0°C to 70°C UNITS MIN/MAX
85°C
Filter Select = 9 MHz: at 5.1 MHz 75 dB
Filter Select = 16 MHz: at 11 MHz 74 dB
MUX Isolation
Filter Select = 35 MHz: at 27 MHz 74 dB
Filter Select = Bypass: at 60 MHz 75 dB
Output impedance f = 10 MHz 0.8 Ω
DC PERFORMANCE
Output offset voltage Bias = dc 20 70 80 85 mV Max
Average offset voltage drift Bias = dc 20 μV/°C
Bias = dc + 250 mV, V
I
= 0 V 255 210/300 200/310 190/320 mV Min/Max
Bias output voltage
Bias = ac 1.05 0.9/1.2 0.85/1.25 0.85/1.25 V Min/Max
Sync tip clamp voltage Bias = ac STC, clamp voltage 250 190/310 180/320 175/325 mV Min/Max
Input bias current Bias = dc - implies Ib out of the pin –0.6 –4 –5 –5 μA Max
Average bias current drift Bias = dc 10 nA/°C
Bias = ac STC, low bias 1.6 0.6/3.3 0.5/3.5 0.4/3.6 μA Min/Max
Sync tip clamp bias current Bias = ac STC, mid bias 5.8 4.3/8.2 4.1/8.4 4/8.5 μA Min/Max
Bias = ac STC, high bias 7.4 6.2/10.8 6/11 5.9/11.1 μA Min/Max
INPUT CHARACTERISTICS
Input voltage range Bias = dc - ensured by output 0/2.1 0/1.8 0/1.7 0/1.6 V Min/Max
Bias = ac bias mode 21 kΩ
Input resistance
Bias = dc, dc + 250 mV, ac STC 3 MΩ
Input capacitance 2 pF
OUTPUT CHARACTERISTICS
R
L
= 150 Ω to Midrail 2.1 V
High output voltage swing
R
L
= 150 Ω to GND 2.1 1.8 1.7 1.6 V Min
(limited by input voltage with
R
L
= 75 Ω to Midrail 2.1 V
gain = 0 dB)
R
L
= 75 Ω to GND 2.1 V
R
L
= 150 Ω to Midrail 0.14 0.24 0.27 0.28 V Max
R
L
= 150 Ω to GND 0.09 0.17 0.2 0.21 V Max
Low output voltage swing
R
L
= 75 Ω to Midrail 0.24 0.33 0.36 0.37 V Max
R
L
= 75 Ω to GND 0.09 0.17 0.2 0.21 V Max
R
L
= 10 Ω to GND, sourcing 70 mA
Output current
R
L
= 10 Ω to Midrail, sinking 70 45 42 40 mA Min
4 Copyright © 2005–2012, Texas Instruments Incorporated
![](https://csdnimg.cn/release/download_crawler_static/87239992/bg5.jpg)
THS7353
www.ti.com
SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS, V
S+
= 3.3 V (continued)
R
L
= 150 Ω to GND, Filter Select = 9 MHz, Input Bias = dc, Gain Adjust pin shorted to the output pin (unless otherwise
noted).
TYP OVERTEMPERATURE
PARAMETER TEST CONDITIONS
–40°C to
25°C 25°C 0°C to 70°C UNITS MIN/MAX
85°C
POWER SUPPLY
Maximum operating voltage 3.3 5.5 5.5 5.5 V Max
Minimum operating voltage 3.3 2.7 2.7 2.7 V Min
Maximum quiescent current Per channel V
I
= 400 mV 5.9 7.1 7.3 7.4 mA Max
Minimum quiescent current Per channel V
I
= 400 mV 5.9 4.7 4.5 4.4 mA Min
Total quiescent current All channels ON, V
I
= 400 mV
(3)
16.2 mA
Power supply rejection
V
S+
= 3.5 V to 3.1 V 48 40 38 37 dB Min
(+PSRR)
DISABLE CHARACTERISTICS
Quiescent current All 3 channels disabled
(4)
0.1 μA
Turn-on time delay (t
ON
) 5 μs
Time reaches 50% of final value after
I
2
C control is completed
Turn-on time delay (t
OFF
) 2 μs
DIGITAL CHARACTERISTICS
(5)
High-level input voltage (V
IH
) 2.3 V Typ
Low-level input voltage (V
IL
) 1.0 V Typ
(3) Due to sharing of internal bias circuitry, the quiescent current, with all channels operating, is less than the single individual channel
quiescent currents added together.
(4) Note that the I
2
C circuitry is still active while in Disable mode. The current shown is while there is no activity with the THS7353 I
2
C
circuitry.
(5) Standard CMOS logic.
Copyright © 2005–2012, Texas Instruments Incorporated 5
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