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TI-DRV602.pdf
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TI-DRV602.pdf
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DRV602
LEFT
RIGHT
-
+
-
+
DAC
DAC
SOC
DRV602
www.ti.com
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
DirectPath™, Pop-Free 3Vrms Line Driver with Adjustable Gain
Check for Samples: DRV602
Designed using TI's patented DirectPath™
1
FEATURES
technology, the DRV602 is capable of driving 3Vrms
234
• DirectPath™
into a 2.5kΩ load with 5V supply voltage. The device
– Eliminates Pop/Clicks
has differential inputs and uses external gain setting
resistors, that supports a gain range of ±1V/V to
– Eliminates Output DC-Blocking Capacitors
±10V/V. The use of external gain resistors also allows
– Provides Flat Frequency Response
the implementation of a 2nd order low pass filter to
20Hz–20kHz
compliment DAC's and SOC converters. The line
• Low Noise and THD
output of the DRV602 has ±8kV IEC ESD protection.
The DRV602 (referred to as the '602) has built-in
– SNR > 102 dB
shutdown control for pop-free on/off control.
– Typical V
N
< 15 mVms
Using the DRV602 in audio products can reduce
– THD+N < 0.05% 20 Hz–20 kHz
component count compared to traditional methods of
• Output Voltage into 2.5-kΩ Load
generating a 3Vrms output. The DRV602 doesn't
– 2 Vrms with 3.3-V Supply Voltage
require a power supply greater than 5V to generate
its 8.5V
PP
output, nor does it require a split rail power
– 3 Vrms with 5-V Supply Voltage
supply. The DRV602 integrates its own charge pump
• 3Vrms Output Voltage into 2.5 kΩ Load With
to generate a negative supply rail that provides a
5V Supply Voltage
clean, pop-free ground biased 3Vrms output.
• Differential Input
The DRV602 is available in a 14 pin TSSOP
package.
APPLICATIONS
If higher SNR, trimmed DC-offset and external
• Set-Top Boxes
undervoltage-mute functions are beneficial in the
• PDP / LCD TV
application, TI recommends the footprint compatible
• Blu-ray Disc™, DVD-Players
DRV603 (SLOS617).
• Home Theater in a Box
For a stereo line and stereo HP driver see DRV604
(SLOS659).
DESCRIPTION
The DRV602PW is a 3Vrms pop-free stereo line
driver designed to allow the removal of the output
dc-blocking capacitors for reduced component count
and cost. The device is ideal for single supply
electronics where size and cost are critical design
parameters.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DirectPath, TI FilterPro are trademarks of Texas Instruments.
3Blu-ray Disc is a trademark of Blu-ray Disc Association.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
+INR
2
3
4
-INR
OUTR
SGND
5
6
7 8
EN
PVSS
CN
9
10
11
12
13
14
CP
PVDD
PGND
OUTL
-INL
+INL
ChargePump
NC
a
DRV602
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PW (TSSOP) PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN
I/O
(1)
DESCRIPTION
NAME TSSOP (PW)
+INR 1 I Right channel OPAMP positive input
–INR 2 I Right channel OPAMP negative input
OUTR 3 O Right channel OPAMP output
SGND 4 I Signal ground
EN 5 I Enable input, active high
PVSS 6 O Supply voltage
CN 7 I/O Charge pump flying capacitor negative terminal
CP 8 I/O Charge pump flying capacitor positive terminal
PVDD 9 I Positive supply
PGND 10 I Power ground
NC 11 No internal connection
OUTL 12 O Left channel OPAMP output
–INL 13 I Left channel OPAMP negative input
+INL 14 I Left channel OPAMP positive input
(1) I = input, O = output, P = power
2 Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
ABSOLUTE MAXIMUM RATINGS
(1) (2)
over operating free-air temperature range
VALUE UNIT
Supply voltage, VDD to GND –0.3 V to 5.5 V
V
I
Input voltage V
SS
– 0.3 to V
DD
+ 0.3 V
R
L
Minimum load impedance > 600 Ω
EN to GND –0.3 to V
DD
+0.3 V
T
J
Maximum operating junction temperature range, –40 to 150 °C
T
stg
Storage temperature range –40 to 150 °C
ESD IEC Contact ESD Protection per IEC6100-4-2, on output pins measured on DRV602EVM ±8 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
DISSIPATION RATINGS
POWER RATING
(1)
POWER RATING
(1)
PACKAGE q
JC
(°/W) q
JA
(°/W)
AT T
A
≤ 25°C AT T
A
≤ 70°C
TSSOP-14 (PW) 35 115
(2)
870mW 348mW
(1) Power rating is determined with a junction temperature of 125°C. This is the point where performance starts to degrade and long-term
reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C
for best performance and reliability.
(2) These data were taken with the JEDEC High-K test printed circuit board (PCB). For the JEDEC low-K test PCB, the q
JA
is 185°C.
ORDERING INFORMATION
T
A
PACKAGE
(1)
DESCRIPTION
-40°C to 85°C DRV602PW 14-Pin TSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
MIN TYP MAX UNIT
V
DD
Supply voltage, DC Supply Voltage 3 3.3 5.5 V
V
IH
High-level input voltage EN 60 % of VDD
V
IL
Low-level input voltage EN 40 % of VDD
T
A
Operating free-air temperature –40 85 °C
ELECTRICAL CHARACTERISTICS
T
A
= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
OS
| Output offset voltage V
DD
= 3 V to 5 V, Voltage follower - gain = 1 5 mV
PSRR Supply Rejection Ratio V
DD
= 3.3 V to 5 V 88 dB
V
OH
High-level output voltage V
DD
= 3.3 V, R
L
= 2.5 kΩ 3.10 V
V
OL
Low-level output voltage V
DD
= 3.3 V, R
L
= 2.5 kΩ –3.05 V
|I
IH
| High-level input current (EN) V
DD
= 5 V, V
I
= V
DD
1 µA
|I
IL
| Low-level input current (EN) V
DD
= 5 V, V
I
= 0 V 1 µA
V
DD
= 3.3 V, No load, EN = V
DD
8 11
mA
I
DD
Supply Current V
DD
= 5 V, No load, EN = V
DD
12.5 20
Shutdown mode, Vdd = 3 V to 5 V 2 mA
Copyright © 2008–2010, Texas Instruments Incorporated 3
Product Folder Link(s): DRV602
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