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TI-TLV320AIC3253.pdf
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TI-TLV320AIC3253.pdf
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DRC
Left
DAC
+
+
*
DRC
Right
DAC
*
DAC Signal Proc.
Vol. Ctrl
Vol. Ctrl
-6...+29dB
1dB steps
-6...+29dB
1dB steps
HPL
HPR
Data Interface
miniDSP
SPI / I2C
Control Block
Pin Muxing/ Clock Routing
Secondary
I
2
S IF
Primary
I
2
S Interface
Interrupt
Ctrl
ALDO
PLL
Mic Bias
INL
INR
SPI_Select
Micbias
Supplies
AVss
DVss
IOVss
DVdd
IOVdd
SDA/MOSI
DMCLK/
MFP4
DMDIN/
MFP3
MCLK
DOUT/MFP2
DIN/MFP1
BCLK
WCLK
AVdd
LDOin
Dig.
Mic IF
GPIO
(YZK Pkg only)
Reset
miniDSP
DAC Signal Proc.
ADC Signal Proc.
Ref
Ref
SCL/SS
TLV320AIC3253
www.ti.com
SLOS631 –MARCH 2010
Ultra Low Power Stereo Audio Codec With Embedded miniDSP
Check for Samples: TLV320AIC3253
1
FEATURES
APPLICATIONS
• Mobile Handsets
2
• Stereo Audio DAC with 100dB SNR
• Communication
• 4.1mW Stereo 48ksps Playback
• Portable Computing
• PowerTune™
• Extensive Signal Processing Options
DESCRIPTION
• Embedded miniDSP
The TLV320AIC3253 (sometimes referred to as the
• Stereo Digital Microphone Input
AIC3253) is a flexible, low-power, low-voltage stereo
• Stereo Headphone Outputs
audio codec with digital microphone inputs and
programmable outputs, PowerTune capabilities,
• Low Power Analog Bypass Mode
fully-programmable miniDSP, fixed predefined and
• Programmable PLL
parameterizable signal processing blocks, integrated
• Integrated LDO
PLL, integrated LDO and flexible digital interfaces.
Extensive register-based control of power,
• 2.7mm × 2.7mm WCSP or 4mm × 4mm QFN
input/output channel configuration, gains, effects,
Package
pin-multiplexing and clocks is included, allowing the
device to be precisely targeted to its application.
Figure 1. Simplified Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerTune is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2010, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV320AIC3253
SLOS631 –MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
Combined with the advanced PowerTune technology, the device can cover operations from 8kHz mono voice
playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC3253 consists of a stereo digital microphone PDM interface (not available
when using SPI control interface) typically used at 64Fs or 128Fs.
The playback path offers signal processing blocks for filtering and effects, true differential output signal, flexible
mixing of DAC and analog input signals as well as programmable volume controls. The TLV320AIC3253
contains two high-power output drivers which can be configured in multiple ways, including stereo, and mono
BTL. The integrated PowerTune technology allows the device to be tuned to just the right power-performance
trade-off. Mobile applications frequently have multiple use cases requiring very low-power operation while being
used in a mobile environment. When used in a docked environment power consumption typically is less of a
concern while lowest possible noise is important. With PowerTune the TLV320AIC3253 can address both cases.
The voltage supply range for the TLV320AIC3253 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To
ease system-level design, a low-dropout regulator (LDO) is integrated to generate the appropriate analog supply
from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are supported in the range of 1.1V–3.6V.
The required internal clock of the TLV320AIC3253 can be derived from multiple sources, including the MCLK pin,
the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived
from the MCLK pin, the BCLK or GPIO pins. Although using the internal, fractional PLL ensures the availability of
a suitable clock signal, it is not recommended for the lowest power settings. The PLL is highly programmable and
can accept available input clocks in the range of 512kHz to 50MHz.
The device is available in the 2.7mm × 2.7mm WCSP or the 4mm × 4mm QFN package.
2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3253
B
C
D
E
A
1 2 3 4 5
DVss
DVdd
IOVdd (24)
SDA/MOSI
DMCLK/MFP4
HPR
LDOin
HPL
DOUT/MFP2
DIN/MFP1
WCLK
BCLK
MCLK (1)
MICBIAS
REF
INR
INL
AVss
AVdd
DMDIN/MFP3
SCL/SS
RESET
SPI_SELECT
IOVss
TLV320AIC3253
www.ti.com
SLOS631 –MARCH 2010
Package and Signal Descriptions
Packaging/Ordering Information
PRODUCT PACKAGE PACKAGE OPERATING ORDERING TRANSPORT MEDIA,
DESIGNATOR TEMPERATURE NUMBER QUANTITY
RANGE
S-XBGA-N25 YZK –40°C to 85°C TLV320AIC3253IYZKT Tape and Reel, 250
TLV320AIC3253IYZKR Tape and Reel, 3000
TLV320AIC3253
S-PQFP-N RGE –40°C to 85°C TLV320AIC3253IRGET Tape and Reel, 250
TLV320AIC3253IRGER Tape and Reel, 3000
Pin Assignments
space
space
Figure 2. S-XBGA-N25 (YZK) Package, Bottom View
Figure 3. S-PQFP-N (RGE) Package, Bottom View
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TLV320AIC3253
TLV320AIC3253
SLOS631 –MARCH 2010
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
NAME TYPE DESCRIPTION
(1) (2)
QFN PIN WCSP
BALL
1 A1 MCLK I Master Clock Input
2 B2 BCLK IO Audio serial data bus (primary) bit clock
3 B3 WCLK IO Audio serial data bus (primary) word clock
4 A2 DIN/MFP1 I Primary function
Audio serial data bus data input
Secondary function
Digital Microphone Input
General Purpose Input
5 A3 DOUT/MFP2 O Primary
Audio serial data bus data output
Secondary
General Purpose Output
Clock Output
INT1 Output
INT2 Output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
6 A5 DMDIN/ I Primary (SPI_Select = 1)
MFP3/
SPI serial clock
SCLK
Secondary: (SPI_Select = 0)
Digital microphone input
Headset detect input
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) DAC/common word clock input
Audio serial data bus (secondary) ADC word clock input
Audio serial data bus (secondary) data input
General Purpose Input
7 A4 SCL/ I I
2
C interface serial clock (SPI_Select = 0)
SS SPI interface mode chip-select signal (SPI_Select = 1)
8 B4 SDA/ MOSI I I
2
C interface mode serial data input (SPI_Select = 0)
SPI interface mode serial data input (SPI_Select = 1)
9 B5 DMCLK/ O Primary (SPI_Select = 1)
MFP4/
Serial data output
MISO
Secondary (SPI_Select = 0) Multifunction pin #4 (MFP4) options are only available
using I
2
C
Digital microphone clock output
General purpose output
CLKOUT output
INT1 output
INT2 output
Audio serial data bus (primary) ADC word clock output
Audio serial data bus (secondary) data output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
10 C5 HPR O Right high-power output driver
11 D5 LDOIN/ Power LDO Input supply and Headphone Power supply 1.9V– 3.6V
HPVDD
12 D4 HPL O Left high power output driver
(1) For multiple BGA Balls assigned to the same pin-name, it is necessary to connect them on the PCB.
(2) For multiple BGA Balls assigned to the same pin-name, it is recommended to connect them on the PCB.
4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3253
TLV320AIC3253
www.ti.com
SLOS631 –MARCH 2010
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME TYPE DESCRIPTION
(1) (2)
QFN PIN WCSP
BALL
13 D3 AVDD Power Analog voltage supply 1.5V–1.95V
Input when A-LDO disabled,
Filtering output when A-LDO enabled
14 E4 AVSS Ground Analog ground supply
15 E5 INL I Left Analog Bypass Input
16 E3 INR I Right Analog Bypass Input
17 E2 REF O Reference voltage output for filtering
18 D2 MICBIAS O Microphone bias voltage output
19 E1 SPI_ SELECT I Control mode select pin ( 1 = SPI, 0 = I2C )
20 C2 RESET I Reset (active low)
21 D1 DVSS Ground Digital Ground and Chip-substrate
22 C1 DVDD Power Digital voltage supply 1.26V–1.95V
23 B1 IOVSS Ground I/O ground supply
24 C3 IOVDD Power I/O voltage supply 1.1V – 3.6V
n/a C4 GPIO/MFP5 I Primary
General Purpose digital IO
Secondary
CLKOUT Output
INT1 Output
INT2 Output
Audio serial data bus ADC word clock output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Digital microphone clock output
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TLV320AIC3253
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