TI-CD74HCT4020.pdf资源-CSDN文库

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Data sheet acquired from Harris Semiconductor

SCHS201C

Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Negative Edge Clocking

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC4020 and ’HCT4020 are 14-stage ripple-carry

binary counters. All counter stages are master-slave ﬂip-

ﬂops. The state of the stage advances one count on the

negative clock transition of each input pulse; a high voltage

level on the MR line resets all counters to their zero state. All

inputs and outputs are buffered.

Pinout

CD54HC4020, CD54HCT4020

(CERDIP)

CD74HC4020, CD74HCT4020

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4020F3A -55 to 125 16 Ld CERDIP

CD54HCT4020F3A -55 to 125 16 Ld CERDIP

CD74HC4020E -55 to 125 16 Ld PDIP

CD74HC4020M -55 to 125 16 Ld SOIC

CD74HC4020MT -55 to 125 16 Ld SOIC

CD74HC4020M96 -55 to 125 16 Ld SOIC

CD74HCT4020E -55 to 125 16 Ld PDIP

CD74HCT4020M -55 to 125 16 Ld SOIC

CD74HCT4020MT -55 to 125 16 Ld SOIC

CD74HCT4020M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

GND

‘

February 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4020, CD74HC4020,

CD54HCT4020, CD74HCT4020

High-Speed CMOS Logic

14-Stage Binary Counter

[

/Title

(

CD74

C402

D74

CT40

Sub-

ect

(

High

peed

MOS

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For V

< -0.5V or V

> V

+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For V

< -0.5V or V

> V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For V

> -0.5V or V

< V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC V

or Ground Current, I

CC or

GND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (T

) . . . . . . . . . . . . . . . . . . . . . -55

C to 125

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

, V

. . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 1) θ

(

C/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . .-65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS

(V)

C -40

C TO 85

C -55

C TO 125

UNITSV

(V) I

(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

or V

-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

or V

0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current

GND

-6--±0.1 - ±1-±1 µA

Quiescent Device

Current

GND

0 6 - - 8 - 80 - 160 µA

CD54HC4020, CD74HC4020, CD54HC4020, CD74HCT4020

剩余15页未读，继续阅读

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