TI-CD74HCT4046A.pdf资源-CSDN文库

需积分: 5 144 浏览量 2022-11-30 23:37:59 上传评论 4 收藏 1.15MB PDF 举报

资源推荐

资源详情

资源评论

Data sheet acquired from Harris Semiconductor

SCHS204J

Features

• Operating Frequency Range

- Up to 18MHz (Typ) at V

= 5V

- Minimum Center Frequency of 12MHz at V

= 4.5V

• Choice of Three Phase Comparators

- EXCLUSIVE-OR

- Edge-Triggered JK Flip-Flop

- Edge-Triggered RS Flip-Flop

• Excellent VCO Frequency Linearity

• VCO-Inhibit Control for ON/OFF Keying and for Low

Standby Power Consumption

• Minimal Frequency Drift

• Operating Power Supply Voltage Range

- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V

- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at VOL, VOH

Applications

• FM Modulation and Demodulation

• Frequency Synthesis and Multiplication

• Frequency Discrimination

• Tone Decoding

• Data Synchronization and Conditioning

• Voltage-to-Frequency Conversion

• Motor-Speed Control

Description

The ’HC4046A and ’HCT4046A are high-speed silicon-gate

CMOS devices that are pin compatible with the CD4046B of

the “4000B” series. They are specified in compliance with

JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop

circuits that contain a linear voltage-controlled oscillator

(VCO) and three different phase comparators (PC1, PC2 and

PC3). A signal input and a comparator input are common to

each comparator.

The signal input can be directly coupled to large voltage

signals, or indirectly coupled (with a series capacitor) to small

voltage signals. A self-bias input circuit keeps small voltage

signals within the linear region of the input amplifiers. With a

passive low-pass filter, the 4046A forms a second-order loop

PLL. The excellent VCO linearity is achieved by the use of

linear op-amp techniques.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4046AF3A -55 to 125 16 Ld CERDIP

CD54HCT4046AF3A -55 to 125 16 Ld CERDIP

CD74HC4046AE -55 to 125 16 Ld PDIP

CD74HC4046AM -55 to 125 16 Ld SOIC

CD74HC4046AMT -55 to 125 16 Ld SOIC

CD74HC4046AM96 -55 to 125 16 Ld SOIC

CD74HC4046ANSR -55 to 125 16 Ld SOP

CD74HC4046APWR -55 to 125 16 Ld TSSOP

CD74HC4046APWT -55 to 125 16 Ld TSSOP

CD74HCT4046AE -55 to 125 16 Ld PDIP

CD74HCT4046AM -55 to 125 16 Ld SOIC

CD74HCT4046AMT -55 to 125 16 Ld SOIC

CD74HCT4046AM96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

February 1998 - Revised December 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4046A, CD74HC4046A,

CD54HCT4046A, CD74HCT4046A

High-Speed CMOS Logic

Phase-Locked Loop with VCO

[ /Title

(CD74

HC404

6A,

CD74

HCT40

46A)

/Sub-

ject

(High-

Speed

CMOS

General Description

VCO

The VCO requires one external capacitor C1 (between C1

and C1

) and one external resistor R1 (between R

and

GND) or two external resistors R1 and R2 (between R

and

GND, and R

and GND). Resistor R1 and capacitor C1

determine the frequency range of the VCO. Resistor R2

enables the VCO to have a frequency offset if required. See

logic diagram, Figure 1.

The high input impedance of the VCO simpliﬁes the design

of low-pass ﬁlters by giving the designer a wide choice of

resistor/capacitor ranges. In order not to load the low-pass

ﬁlter, a demodulator output of the VCO input voltage is

provided at pin 10 (DEM

OUT

). In contrast to conventional

techniques where the DEM

OUT

voltage is one threshold

voltage lower than the VCO input voltage, here the DEM

OUT

voltage equals that of the VCO input. If DEM

OUT

is used, a

load resistor (R

) should be connected from DEM

OUT

GND; if unused, DEM

OUT

should be left open. The VCO

output (VCO

OUT

) can be connected directly to the

comparator input (COMP

), or connected via a frequency-

divider. The VCO output signal has a speciﬁed duty factor of

50%. A LOW level at the inhibit input (INH) enables the VCO

and demodulator, while a HIGH level turns both off to

minimize standby power consumption.

Phase Comparators

The signal input (SIG

) can be directly coupled to the self-

biasing ampliﬁer at pin 14, provided that the signal swing is

between the standard HC family input logic levels.

Capacitive coupling is required for signals with smaller

swings.

Phase Comparator 1 (PC1)

This is an Exclusive-OR network. The signal and comparator

input frequencies (f

) must have a 50% duty factor to obtain

the maximum locking range. The transfer characteristic of

PC1, assuming ripple (f

= 2f

) is suppressed, is:

DEMOUT

=(V

/π)(φSIG

- φCOMP

) where V

DEMOUT

is the demodulator output at pin 10; V

DEMOUT

PC1OUT

(via low-pass ﬁlter).

The average output voltage from PC1, fed to the VCO input

via the low-pass ﬁlter and seen at the demodulator output at

pin 10 (V

DEMOUT

), is the resultant of the phase differences

of signals (SIG

) and the comparator input (COMP

)as

shown in Figure 2. The average of V

DEM

is equal to 1/2

when there is no signal or noise at SIG

, and with this

input the VCO oscillates at the center frequency (f

Typical waveforms for the PC1 loop locked at f

are shown

in Figure 3.

FIGURE 1. LOGIC DIAGRAM

DEM

OUT

PC2

OUT

GND

PCP

OUT

PC3

OUT

PC1

OUT

DOWN

INH

VCO

OUT

COMP

SIG

REF

674314

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

The frequency capture range (2f

) is deﬁned as the

frequency range of input signals on which the PLL will lock if

it was initially out-of-lock. The frequency lock range (2f

)is

deﬁned as the frequency range of input signals on which the

loop will stay locked if it was initially in lock. The capture

range is smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass ﬁlter

characteristics and can be made as large as the lock range.

This conﬁguration retains lock behavior even with very noisy

input signals. Typical of this type of phase comparator is that

it can lock to input frequencies close to the harmonics of the

VCO center frequency.

Phase Comparator 2 (PC2)

This is a positive edge-triggered phase and frequency

detector. When the PLL is using this comparator, the loop

is controlled by positive signal transitions and the duty

factors of SIG

and COMP

are not important. PC2

comprises two D-type ﬂip-ﬂops, control-gating and a three-

state output stage. The circuit functions as an up-down

counter (Figure 1) where SIG

causes an up-count and

COMP

a down-count. The transfer function of PC2,

assuming ripple (f

= f

) is suppressed, is:

DEMOUT

=(V

/4π)(φSIG

- φCOMP

) where

DEMOUT

is the demodulator output at pin 10;

DEMOUT

PC2OUT

(via low-pass ﬁlter).

The average output voltage from PC2, fed to the VCO via the

low-pass ﬁlter and seen at the demodulator output at pin 10

DEMOUT

), is the resultant of the phase differences of

SIG

and COMP

as shown in Figure 4. Typical waveforms

for the PC2 loop locked at f

are shown in Figure 5.

When the frequencies of SIG

and COMP

are equal but

the phase of SIG

leads that of COMP

, the p-type output

driver at PC2

OUT

is held “ON” for a time corresponding to

the phase difference (φ

DEMOUT

). When the phase of SIG

lags that of COMP

, the n-type driver is held “ON”.

When the frequency of SIG

is higher than that of

COMP

, the p-type output driver is held “ON” for most of

the input signal cycle time, and for the remainder of the

cycle both n- and p-type drivers are “OFF” (three-state). If

the SIG

frequency is lower than the COMP

frequency,

then it is the n-type driver that is held “ON” for most of the

cycle. Subsequently, the voltage at the capacitor (C2) of

the low-pass ﬁlter connected to PC2

OUT

varies until the

signal and comparator inputs are equal in both phase and

FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:

DEMOUT

= V

PC1OUT

= (V

/π) (φSIG

φCOMP

); φ

DEMOUT

=(φSIG

- φCOMP

)

DEMOUT (AV)

1/2 V

DEMOUT

180

FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 1, LOOP LOCKED AT f

SIG

COMP

VCO

OUT

PC1

OUT

VCO

GND

FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:

DEMOUT

= V

PC2OUT

= (V

/4π) (φSIG

- φCOMP

);

DEMOUT

=(φSIG

- φCOMP

)

DEMOUT (AV)

1/2 V

-360

DEMOUT

360

FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 2, LOOP LOCKED AT f

SIG

COMP

VCO

OUT

PC2

OUT

VCO

GND

PCP

OUT

HIGH IMPEDANCE OFF - STATE

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

frequency. At this stable point the voltage on C2 remains

constant as the PC2 output is in three-state and the VCO

input at pin 9 is a high impedance. Also in this condition,

the signal at the phase comparator pulse output (PCP

OUT

)

is a HIGH level and so can be used for indicating a locked

condition.

Thus, for PC2, no phase difference exists between SIG

and COMP

over the full frequency range of the VCO.

Moreover, the power dissipation due to the low-pass ﬁlter is

reduced because both p- and n-type drivers are “OFF” for

most of the signal input cycle. It should be noted that the

PLL lock range for this type of phase comparator is equal to

the capture range and is independent of the low-pass ﬁlter.

With no signal present at SIG

, the VCO adjusts, via PC2,

to its lowest frequency.

Phase Comparator 3 (PC3)

This is a positive edge-triggered sequential phase

detector using an RS-type flip-flop. When the PLL is using

this comparator, the loop is controlled by positive signal

transitions and the duty factors of SIG

and COMP

are

not important. The transfer characteristic of PC3,

assuming ripple (f

= f

) is suppressed, is:

DEMOUT

=(V

/2p) (fSIG

- fCOMP

) where

DEMOUT

is the demodulator output at pin 10; V

DEMOUT

= V

PC3OUT

(via low-pass filter).

The average output from PC3, fed to the VCO via the low-

pass filter and seen at the demodulator at pin 10

DEMOUT

), is the resultant of the phase differences of

SIG

and COMP

as shown in Figure 6. Typical

waveforms for the PC3 loop locked at f

are shown in

Figure 7.

The phase-to-output response characteristic of PC3

(Figure 6) differs from that of PC2 in that the phase angle

between SIG

and COMP

varies between 0

and 360

and is 180

at the center frequency. Also PC3 gives a

greater voltage swing than PC2 for input phase differences

but as aconsequence the ripple content of the VCO input

signal is higher. With no signal present at SIG

, the VCO

adjusts, via PC3, to its highest frequency.

The only difference between the HC and HCT versions is the

input level speciﬁcation of the INH input. This input disables

the VCO section. The comparator’s sections are identical, so

that there is no difference in the SIG

(pin 14) or COMP

(pin 3) inputs between the HC and the HCT versions.

FIGURE 6. PHASE COMPARATOR 3: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:

DEMOUT

= V

PC3OUT

= (V

/2π) (φSIG

- φCOMP

);

DEMOUT

= (φSIG

- φCOMP

)

DEMOUT (AV)

1/2 V

180

DEMOUT

360

FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 3, LOOP LOCKED AT f

SIG

COMP

VCO

OUT

PC3

OUT

VCO

GND

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

剩余33页未读，继续阅读

评论收藏

内容反馈

不觉明了

粉丝: 3153
资源: 5416

TI-CD74HCT4046A.pdf

TI-CD74HCT7046A.pdf

TI-CD74HCT297.pdf

TI-CD74HCT85.pdf

TI-CD74HCT688.pdf

TI-CD74HCT221.pdf

TI-CD74HCT423.pdf

TI-CD74HCT4538.pdf

TI-CD74HCT4040.pdf

TI-CD74HCT4060.pdf

TI-CD74HCT4020.pdf

TI-CD74HCT4024.pdf

TI-CD74HCT4520.pdf

TI-CD74HCT154.pdf

TI-CD74HCT4543.pdf

TI-CD74HCT237.pdf

TI-CD74HCT139.pdf

TI-CD74HCT42.pdf

TI-CD54HCT4051.pdf

TI-CD54HCT238.pdf

相关实用应用程序（Windows可用）

免费可用的ChatGPT网页版.zip

ChatGPT使用总结：150个ChatGPT提示词模板（完整版）

chromedriver-win64.zip

全国计算机二级WPSoffice精选350道选择题题库（含答案）.pdf

哈尔滨工业大学-ChatGPT调研报告-2023.3.6-94页.pdf

农村公交与异构无人机协同配送优化

李飞飞自传 我看见的世界 The World I see

4个亲测好用的ChatGPT4渠道

2023泛娱乐社交出海手册-ZEGO即构科技

最新资源

李飞飞自传我看见的世界 The World I see