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TI-TPS51216-EP.pdf
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V5IN
TPS51216
S3
S5
VREF
VBST
DRVH
SW
DRVL
8
10
REFIN
PGND
7
19
GND
MODE
18 TRIP
20
9
2
3
PGOOD
VDDQSNS
VLDOIN
VTT
1
4
5
VTTSNS
VTTGND
VTTREF
UDG-10138
VDDQ
VTT
PGND
S3
S5
PGND
5VIN
PGND
VIN
VTTREF
AGND
AGND
Powergood
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TPS51216-EP
SLUSCA7 –NOVEMBER 2015
TPS51216-EP Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous
Buck Controller, 2-A LDO, Buffered Reference
1 Features 2 Applications
1
• Synchronous Buck Controller (VDDQ)
• DDR2/DDR3/DDR3L Memory Power Supplies
• SSTL_18, SSTL_15, SSTL_135, and HSTL
– Conversion Voltage Range: 3 to 28 V
Termination
– Output Voltage Range: 0.7 to 1.8 V
– 0.8% V
REF
Accuracy
3 Description
– D-CAP™ Mode for Fast Transient Response
The TPS51216-EP provides a complete power supply
– Selectable 300-kHz/400-kHz Switching
for DDR2, DDR3 and DDR3L memory systems in the
Frequencies
lowest total cost and minimum space. It integrates a
synchronous buck regulator controller (VDDQ) with a
– Optimized Efficiency at Light and Heavy Loads
2-A sink/source tracking LDO (VTT) and buffered low
With Auto-Skip Function
noise reference (VTTREF). The TPS51216-EP
– Supports Soft-Off in S4/S5 States
employs D-CAP™ mode coupled with 300 kHz/400
– OCL/OVP/UVP/UVLO Protections
kHz frequencies for ease-of-use and fast transient
response. The VTTREF tracks VDDQ/2 within
– Powergood Output
excellent 0.8% accuracy. The VTT, which provides 2-
• 2-A LDO (VTT), Buffered Reference (VTTREF)
A sink/source peak current capabilities, requires only
– 2-A (Peak) Sink and Source Current
10-μF of ceramic capacitance. In addition, a
dedicated LDO supply input is available.
– Requires Only 10-μF of Ceramic Output
Capacitance
The TPS51216-EP provides rich useful functions as
– Buffered, Low Noise, 10-mA VTTREF Output
well as excellent power supply performance. It
supports flexible power state control, placing VTT at
– 0.8% VTTREF, 20-mV VTT Accuracy
high-Z in S3 and discharging VDDQ, VTT, and
– Support High-Z in S3 and Soft-Off in S4/S5
VTTREF (soft-off) in S4/S5 state.
• Thermal Shutdown
Device Information
(1)
• 20-Pin, 3 mm × 3 mm, WQFN Package
PART NUMBER PACKAGE BODY SIZE (NOM)
• Supports Defense, Aerospace, and Medical
TPS51216-EP WQFN (20) 3.00 mm × 3.00 mm
Applications
(1) For all available packages, see the orderable addendum at
– Controlled Baseline
the end of the data sheet.
– One Assembly/Test Site
– One Fabrication Site
Application Diagram
– Available in Military (–55°C to 125°C)
Temperature Range
(1)
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
(1) Additional temperature ranges available - contact factory
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS51216-EP
SLUSCA7 –NOVEMBER 2015
www.ti.com
Table of Contents
8.3 Feature Description................................................. 15
1 Features.................................................................. 1
8.4 Device Functional Modes........................................ 17
2 Applications ........................................................... 1
9 Application and Implementation ........................ 18
3 Description ............................................................. 1
9.1 Application Information............................................ 18
4 Revision History..................................................... 2
9.2 Typical Application ................................................. 21
5 Description (continued)......................................... 3
10 Power Supply Recommendations ..................... 23
6 Pin Configuration and Functions......................... 3
11 Layout................................................................... 24
7 Specifications......................................................... 4
11.1 Layout Guidelines ................................................. 24
7.1 Absolute Maximum Ratings ...................................... 4
11.2 Layout Example .................................................... 25
7.2 ESD Ratings.............................................................. 4
12 Device and Documentation Support ................. 26
7.3 Recommended Operating Conditions....................... 5
12.1 Community Resources.......................................... 26
7.4 Thermal Information.................................................. 5
12.2 Trademarks........................................................... 26
7.5 Electrical Characteristics........................................... 6
12.3 Electrostatic Discharge Caution............................ 26
7.6 Typical Characteristics.............................................. 8
12.4 Glossary................................................................ 26
8 Detailed Description............................................ 14
13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................. 14
Information ........................................................... 26
8.2 Functional Block Diagram ....................................... 14
4 Revision History
DATE REVISION NOTES
November 2015 * Initial release.
2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS51216-EP
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
17
1819
20
Thermal Pad
VTTSNS
VLDOIN
VTT
VTTGND
VTTREF
VREF
GND
REFIN
VDDQSNS
PGND
DRVL
V5IN
SW
DRVH
VBST
S5
S3
TRIP
MODE
PGOOD
TPS51216-EP
www.ti.com
SLUSCA7 –NOVEMBER 2015
5 Description (continued)
Programmable OCL with low-side MOSFET R
DS(on)
sensing, OVP/UVP/UVLO and thermal shutdown protections
are also available.
The TPS51216-EP is available in a 20-pin, 3 mm × 3 mm, WQFN package and is specified for junction
temperature from –55°C to 125°C.
6 Pin Configuration and Functions
RUK Package
20-Pin WQFN
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
DRVH 14 O High-side MOSFET gate driver output.
DRVL 11 O Low-side MOSFET gate driver output.
GND 7 — Signal ground.
MODE 19 I Connect resistor to GND to configure switching frequency and discharge mode. (See Table 2.)
PGND 10 — Gate driver power ground. R
DS(on)
current sensing input (+).
PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for
REFIN 8 I
stable operation.
SW 13 I/O High-side MOSFET gate driver return. R
DS(on)
current sensing input (–).
S3 17 I S3 signal input. (See Table 1.)
S5 16 I S5 signal input. (See Table 1.)
TRIP 18 I Connect resistor to GND to set OCL at V
TRIP
/ 8. Output 10-μA current at room temperature, T
C
= 4700 ppm/°C.
VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.
VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.
VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application.
VREF 6 O 1.8-V reference output.
VTT 3 O VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability.
VTTGND 4 — Power ground for VTT LDO.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TPS51216-EP
TPS51216-EP
SLUSCA7 –NOVEMBER 2015
www.ti.com
Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability.
VTTSNS 1 I VTT output voltage feedback.
V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers.
Thermal
— — Connect to GND
pad
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
VBST –0.3 36
VBST
(3)
–0.3 6
SW –5 30
Input voltage
(2)
VLDOIN, VDDQSNS, REFIN –0.3 3.6 V
VTTSNS –0.3 3.6
PGND, VTTGND –0.3 0.3
V5IN, S3, S5, TRIP, MODE –0.3 6
DRVH –5 36
DRVH
(3)
–0.3 6
DRVH
(3)
(duty cycle < 1%) –2.5 6
VTTREF, VREF –0.3 3.6
Output voltage
(2)
V
VTT –0.3 3.6
DRVL –0.3 6
DRVL (duty cycle < 1%) –2.5 6
PGOOD –0.3 6
Junction temperature, T
J
–55 135 °C
Storage temperature, T
stg
–55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
7.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
(ESD)
Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-
±500
C101
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS51216-EP
TPS51216-EP
www.ti.com
SLUSCA7 –NOVEMBER 2015
7.3 Recommended Operating Conditions
MIN NOM MAX UNIT
Supply voltage V5IN 4.5 5.5 V
VBST –0.1 33.5
VBST
(1)
–0.1 5.5
SW -3 28
SW
(2)
–4.5 28
Input voltage range V
VLDOIN, VDDQSNS, REFIN –0.1 3.5
VTTSNS –0.1 3.5
PGND, VTTGND –0.1 0.1
S3, S5, TRIP, MODE –0.1 5.5
DRVH –3 33.5
DRVH
(1)
–0.1 5.5
DRVH
(2)
–4.5 33.5
Output voltage range VTTREF, VREF –0.1 3.5 V
VTT –0.1 3.5
DRVL –0.1 5.5
PGOOD –0.1 5.5
T
J
Operating junction temperature –55 125 °C
(1) Voltage values are with respect to the SW terminal.
(2) This voltage should be applied for less than 30% of the repetitive period.
7.4 Thermal Information
TPS51216-EP
THERMAL METRIC
(1)
RUK (WQFN) UNIT
20 PINS
R
θJA
Junction-to-ambient thermal resistance 94.1 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 58.1 °C/W
R
θJB
Junction-to-board thermal resistance 64.3 °C/W
ψ
JT
Junction-to-top characterization parameter 31.8 °C/W
ψ
JB
Junction-to-board characterization parameter 58.0 °C/W
R
θJC(bot)
Junction-to-case (bottom) thermal resistance 5.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TPS51216-EP
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