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TSB82AF15-EP PCI Express-Based IEEE 1394b OHCI Host Controller

1 Features

• PCI Express

™

based 1394b Open Host Controller

Interface (OHCI) link layer controller

– TQFP package simplifies board routing and

eases board inspection

– Stand-alone link layer controller provides

flexibility to interface with a 1394b s400 or a

1394b s800 physical layer controller

• Fully compliant with 1394 OHCI specification,

revision 1.1 and revision 1.2 draft

• Compliant with PCI Express

™

(PCIe) base

specification, revision 1.1. See Section 11.1

• Fully supports provisions of IEEE Std

P1394b-2002, IEEE Std 1394-1995 and IEEE Std

1394a-2000

• EEPROM configuration support to load Global

Unique ID for 1394 fabric

• Utilizes 100-MHz differential PCI Express

™

common reference clock

• Support for D1, D2, D3

hot

• Active-state link power management saves power

when packet activity on the PCI Express

™

link is

idle, using both L0s and L1 states

• Eight 3.3-V multifunction General-Purpose I/O

(GPIO) terminals

• Supports defense, aerospace, and medical

applications:

– Controlled baseline

– One assembly/test site and one fabrication site

– Extended product life cycle and product-change

notification

2 Applications

• Avionics and defense

• Factory automation & control

• Medical

3 Description

The Texas Instruments TSB82AF15-EP is a single-

function PCI Express

™

(PCIe) to PCI local bus

translation bridge, where the PCI bus interface is

internally connected to a 1394b open host controller/

link-layer controller. When the TSB82AF15-EP is

properly configured, this solution provides full PCIe to

1394 link layer controller.

The TSB82AF15-EP simultaneously supports up to

four posted write transactions, four nonposted

transactions, and four completion transactions

pending in each direction at any time. Each posted

write data queue and completion data queue can

store up to 8K bytes of data. The non-posted data

queues can store up to 128 bytes of data.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TSB82AF15-EP 100 pin PZT

14.00 mm × 14.00

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

PCI Express

Transmitter

PCI Express

Receiver

PCI Bus Interface

Configuration and

Memory Register

GPIO

Serial

EEPROM

Reset

Controller

Clock

Generator

Power

Mgmt

1394b OHCI

Simplified Block Diagram

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TSB82AF15-EP

SCPS271 – JULY 2020

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TSB82AF15-EP

SCPS271 – JULY 2020

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 8

6.1 Absolute Maximum Ratings ....................................... 8

6.2 ESD Ratings .............................................................. 8

6.3 Recommended Operating Conditions ........................8

6.4 Thermal Information ...................................................8

6.5 PCIe Differential Transmitter Output Ranges .............8

6.6 PCIe Differential Receiver Input Ranges ..................11

6.7 PCIe Differential Reference Clock Input Ranges .....13

6.8 Electrical Characteristics Over Recommended

Operating Conditions (3.3-V I/O) ................................13

6.9 Switching Characteristics .........................................13

7 Operating Life Deration.................................................14

8 Typical Characteristics................................................. 15

9 Parameter Measurement Information.......................... 16

10 Detailed Description....................................................17

10.1 Overview................................................................. 17

10.2 Functional Block Diagram....................................... 17

10.3 Feature Description.................................................18

10.4 Device Functional Modes........................................30

10.5 Programming.......................................................... 32

10.6 Register Maps.........................................................33

11 Application and Implementation.............................. 164

11.1 Known exceptions to functional specification

(errata).......................................................................164

11.2 Application Information..........................................165

12 Power Supply Recommendations............................167

13 Layout.........................................................................168

13.1 Layout Guidelines................................................. 168

14 Device and Documentation Support........................169

14.1 Device Support..................................................... 169

14.2 Documentation Support........................................ 169

14.3 Receiving Notification of Documentation Updates169

14.4 Support Resources............................................... 169

14.5 Trademarks...........................................................169

14.6 Electrostatic Discharge Caution............................170

14.7 Glossary................................................................170

15 Mechanical, Packaging, and Orderable

Information.................................................................. 171

15.1 Mechanical Data................................................... 172

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE REVISION NOTES

September 2020 * Initial release.

TSB82AF15-EP

SCPS271 – JULY 2020

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Pin Functions

TYPE

(1)

DESCRIPTION

NAME NO.

REFCLK+ 1 DI

Reference clock positive. REFCLK+ and REFCLK- comprise the differential input pair for the

100-MHz system reference clock.

REFCLK- 2 DI

Reference clock negative. REFCLK+ and REFCLK- comprise the differential input pair for the

100-MHz system reference clock.

VSSA 3 P Analog ground.

VDD_33 4 P 3.3-V digital I/O power. Filter from VDDA_33 supply.

LPS 5 O

Link power status. This terminal must be connected to the LPS input terminal of the

connected PHY.

PINT 6 I

PHY interrupt. The connected PHY uses this signal to transfer status and interrupt information

serially to the LLC. This terminal must be connected to the PINT output of the connected PHY.

LINKON 7 I/O

Link-on notification. LINKON is an input to the LLC from the connected PHY that is used to

provide notification that a link-on packet has been received or an event, such as a port

connection, has occurred. This I/O only has meaning when LPS is disabled. This includes the

D0 (uninitialized), D2, and D3 power states. If LINKON becomes active in the D0

(uninitialized), D2, or D3 power state, the TSB82AF15-EP device sets bit 15 (PME_STS) in

the power-management control and status register in the PCI configuration space at offset

48h. This terminal must be connected to the LKON output terminal of the connected PHY.

LREQ 8 O

LLC request. The LLC uses this output to initiate a service request to the connected PHY. This

terminal must be connected to the LREQ input of the connected PHY.

VSS 9 P Digital ground.

PCLK 10 I PHY clock. This terminal must be connected to the PCLK output of the connected PHY.

VDD_15 11 P 1.5-V digital core power for the link. Filter from VDDA_15 supply.

LCLK 12 O LLC clock. This terminal must be connected to the LCLK input terminal of the connected PHY.

VDD_33 13 P 3.3-V digital I/O power. Filter from VDDA_33 supply.

CTL0 14 I/O

Control. CTL[1:0] are bidirectional control bus signals that are used to indicate the phase of

operation of the PHY link interface. Upon a reset of the interface, this bus is driven by the

PHY. When driven by the PHY, information on CTL[1:0] is synchronous to PCLK. When driven

by the link, information on CTL[1:0] is synchronous to LCLK. If not implemented, these

terminals should be left unconnected.

CTL1 15 I/O

Control. CTL[1:0] are bidirectional control bus signals that are used to indicate the phase of

operation of the PHY link interface. Upon a reset of the interface, this bus is driven by the

PHY. When driven by the PHY, information on CTL[1:0] is synchronous to PCLK. When driven

by the link, information on CTL[1:0] is synchronous to LCLK. If not implemented, these

terminals should be left unconnected.

VSS 16 P Digital ground.

D0 17 I/O

Data. D[7:0] comprise a bidirectional data bus that is used to carry 1394 packet data, packet

speed, and grant type information between the PHY and the link. Upon a reset of the

interface, this bus is driven by the PHY. When driven by the PHY, information on D[7:0] is

synchronous to PCLK. When driven by the link, information on D[7:0] is synchronous to LCLK.

If not implemented, these terminals should be left unconnected.

D1 18 I/O D1

D2 19 I/O D2

VDD_15 20 P 1.5-V digital core power for the link. Filter from VDDA_15 supply.

D3 21 I/O D3

D4 22 I/O D4

D5 23 I/O D5

VSS 24 P Digital ground.

D6 25 I/O D6

D7 26 I/O D7

VDD_33 27 P 3.3-V digital I/O power. Filter from VDDA_33 supply.

TSB82AF15-EP

SCPS271 – JULY 2020

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TYPE

(1)

DESCRIPTION

NAME NO.

GPIO0 28 I/O

General-purpose I/O 0. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in