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TI-TPS51200-EP.pdf
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TPS51200
REFIN
VLDOIN
VO
PGND
VOSNS
VIN
PGOOD
GND
EN
REFOUT
3.3 V
IN
PGOOD
SLP_S3
VTTREF
VLDOIN
V
TT
V
DDQ
Copyright © 2016, Texas Instruments Incorporated
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSA48
TPS51200-EP
ZHCSF57 –JUNE 2016
TPS51200-EP 灌灌/拉拉 DDR 终终端端稳稳压压器器
1
1 特特性性
1
• 输入电压:支持 2.5V 和 3.3V 电源轨
• VLDOIN 电压范围:1.1V 至 3.5V
• 具有压降补偿功能的灌电流和拉电流终端稳压器
• 所需最小输出电容为 20μF(通常为 3 × 10μF
MLCC),用于存储器终端 应用 (DDR)
• 用于监视输出稳压的 PGOOD
• EN 输入
• REFIN 输入允许直接或通过电阻分压器灵活进行输
入跟踪
• 远程感测 (VOSNS)
• ±10mA 缓冲基准 (REFOUT)
• 内置软启动,欠压锁定 (UVLO) 和过流限制 (OCL)
• 热关断
• 符合 DDR 和 DDR2 JEDEC 规范
• 支持 DDR3、低功耗 DDR3 和 DDR4 VTT 应用
• 带有散热焊盘的 10 引脚超薄小外形尺寸无引线
(VSON) 封装
• 支支持持国国防防、、航航天天和和医医疗疗 应应用用
– 受控基线
– 一个组装和测试场所
– 一个制造场所
– 支持军用温度范围(-55°C 至 125°C)
– 延长的产品使用寿命周期
– 延长的产品变更通知
– 产品可追溯性
2 应应用用范范围围
• 用于 DDR、DDR2、DDR3、低功耗 DDR3 和
DDR4 的存储器终端稳压器
• 笔记本、台式机和服务器
• 电信和数据通信
• 基站
• 液晶 (LCD) 电视和等离子 (PDP) 电视
• 复印机和打印机
• 机顶盒
3 说说明明
TPS51200-EP 器件是一款灌电流和拉电流双倍数据速
率 (DDR) 终端稳压器,专用于空间问题是重要考量因
素的低输入电压、低成本、低噪声系统。
TPS51200-EP 能够保持快速瞬态响应,最低仅需
20μF 输出电容。TPS51200-EP 支持远程感测功能并
且可满足 DDR、DDR2、DDR3、低功耗 DDR3 和
DDR4 VTT 总线的所有电源要求。
此外,TPS51200-EP 还提供一个开漏 PGOOD 信号
监测输出稳压,提供一个 EN 信号在 S3(挂起至
RA4M)期间针对 DDR 进行 VTT 放电。
TPS51200-EP 采用带散热焊盘的高效散热型 10 引脚
超薄小外形尺寸无引线 (VSON) 封装,无铅且绿色环
保。其额定工作温度范围为 -55°C 至 +125°C。
器器件件信信息息
(1)
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
TPS51200-EP VSON (10) 3.00mm x 3.00mm
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
简简化化的的 DDR 应应用用
2
TPS51200-EP
ZHCSF57 –JUNE 2016
www.ti.com.cn
Copyright © 2016, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用范范围围................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
8 Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical VTT DIMM Applications.............................. 14
8.3 System Examples ................................................... 19
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
10.3 Thermal Design Considerations............................ 26
11 器器件件和和文文档档支支持持 ..................................................... 28
11.1 器件支持................................................................ 28
11.2 文档支持 ............................................................... 28
11.3 接收文档更新通知 ................................................. 28
11.4 社区资源................................................................ 28
11.5 商标 ....................................................................... 28
11.6 静电放电警告......................................................... 28
11.7 Glossary................................................................ 29
12 机机械械、、封封装装和和可可订订购购信信息息....................................... 29
4 修修订订历历史史记记录录
日日期期 修修订订版版本本 注注释释
2016 年 6 月 * 最初发布。
REFIN
VLDOIN
VO
PGND
VOSNS
VIN
PGOOD
GND
EN
REFOUT
Thermal
Pad
10
9
8
7
6
1
2
3
4
5
3
TPS51200-EP
www.ti.com.cn
ZHCSF57 –JUNE 2016
Copyright © 2016, Texas Instruments Incorporated
(1) I = Input, O = Output, G = Ground.
(2) Thermal pad connection. See Figure 31 in the Thermal Design Considerations section for additional information.
5 Pin Configuration and Functions
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
Pin Functions
PIN
I/O
(1)
DESCRIPTION
NAME NO.
EN 7 I
For DDR VTT application, connect EN to SLP_S3. For any other application, use the EN pin
as the ON/OFF function.
GND 8 G Signal ground. Connect to negative terminal of the output capacitor.
PGND
(2)
4 G Power ground output for the LDO.
PGOOD 9 O PGOOD output. Indicates regulation.
REFIN 1 I Reference input.
REFOUT 6 O Reference output. Connect to GND through 0.1-μF ceramic capacitor.
VIN 10 I
2.5-V or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1-μF and
4.7-μF is required.
VLDOIN 2 I Supply voltage for the LDO.
VO 3 O Power output for the LDO.
VOSNS 5 I
Voltage sense input for the LDO. Connect to positive terminal of the output capacitor or the
load.
4
TPS51200-EP
ZHCSF57 –JUNE 2016
www.ti.com.cn
Copyright © 2016, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
Input voltage
(2)
REFIN, VIN, VLDOIN, VOSNS –0.3 3.6
VEN –0.3 6.5
PGND to GND –0.3 0.3
Output voltage
(2)
REFOUT, VO –0.3 3.6
V
PGOOD –0.3 6.5
Operating junction temperature, T
J
–55 150 °C
Storage temperature, T
stg
–55 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
Charged device model (CDM), per JEDEC specification JESD22-C101
(2)
±500
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltages VIN 2.375 3.5 V
Voltage
EN, VLDOIN, VOSNS –0.1 3.5
V
REFIN 0.5 1.8
PGOOD, VO –0.1 3.5
REFOUT –0.1 1.8
PGND –0.1 0.1
Operating junction temperature, T
J
–55 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC
(1)
TPS51200-EP
UNITDRC (VSON)
10 PINS
R
θJA
Junction-to-ambient thermal resistance 55.6 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 84.6 °C/W
R
θJB
Junction-to-board thermal resistance 30 °C/W
ψ
JT
Junction-to-top characterization parameter 5.5 °C/W
ψ
JB
Junction-to-board characterization parameter 30.1 °C/W
R
θJC(bot)
Junction-to-case (bottom) thermal resistance 10.9 °C/W
5
TPS51200-EP
www.ti.com.cn
ZHCSF57 –JUNE 2016
Copyright © 2016, Texas Instruments Incorporated
(1) Ensured by design. Not production tested.
6.5 Electrical Characteristics
Over recommended junction temperature range, V
VIN
= 3.3 V, V
VLDOIN
= 1.8 V, V
REFIN
= 0.9 V, V
VOSNS
= 0.9 V, V
EN
= V
VIN
,
C
OUT
= 3 × 10 μF and circuit shown in (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
I
IN
Supply current T
J
= 25 °C, V
EN
= 3.3 V, no load 0.7 1 mA
I
IN(SDN)
Shutdown current
T
J
= 25 °C, V
EN
= 0 V, V
REFIN
= 0,
no load
65 80
μA
T
J
= 25 °C, V
EN
= 0 V, V
REFIN
> 0.4 V, no
load
200 400
I
LDOIN
Supply current of VLDOIN T
J
= 25 °C, V
EN
= 3.3 V, no load 1 50 μA
I
LDOIN(SDN)
Shutdown current of VLDOIN T
J
= 25 °C, V
EN
= 0 V, no load 0.1 50 μA
INPUT CURRENT
I
REFIN
Input current, REFIN V
EN
= 3.3 V 1 μA
VO OUTPUT
V
VOSNS
Output DC voltage, VO
V
REFOUT
= 1.25 V (DDR1), I
O
= 0 A
1.25 V
–15 15 mV
V
REFOUT
= 0.9 V (DDR2), I
O
= 0 A
0.9 V
–15 15 mV
V
LDOIN
= 1.5 V, V
REFOUT
= 0.75 V (DDR3),
I
O
= 0 A
0.75 V
–15 15 mV
V
VOTOL
Output voltage tolerance to REFOUT –2 A < I
VO
< 2 A –25 25 mV
I
VOSRCL
VO source current Limit
With reference to REFOUT,
V
OSNS
= 90% × V
REFOUT
3 4.5 A
I
VOSNCL
VO sink current Limit
With reference to REFOUT,
V
OSNS
= 110% × V
REFOUT
3.5 5.5 A
I
DSCHRG
Discharge current, VO
V
REFIN
= 0 V, V
VO
= 0.3 V, V
EN
= 0 V, T
J
=
25°C
18 25 Ω
POWERGOOD COMPARATOR
V
TH(PG)
VO PGOOD threshold
PGOOD window lower threshold with
respect to REFOUT
–23.5% –20% –17.5%
PGOOD window upper threshold with
respect to REFOUT
17.5% 20% 23.5%
PGOOD hysteresis 5%
t
PGSTUPDLY
PGOOD start-up delay
Start-up rising edge, VOSNS within 15%
of REFOUT
2 ms
V
PGOODLOW
Output low voltage I
SINK
= 4 mA 0.4 V
t
PBADDLY
PGOOD bad delay
VOSNS is outside of the ±20% PGOOD
window
10 μs
I
PGOODLK
Leakage current
(1)
V
OSNS
= V
REFIN
(PGOOD high
impedance), V
PGOOD
= V
VIN
+ 0.2 V
1 μA
REFIN AND REFOUT
V
REFIN
REFIN voltage range 0.5 1.8 V
V
REFINUVLO
REFIN undervoltage lockout REFIN rising 360 390 420 mV
V
REFINUVHYS
REFIN undervoltage lockout hysteresis 20 mV
V
REFOUT
REFOUT voltage REFIN V
V
REFOUTTOL
REFOUT voltage tolerance to V
REFIN
–10 mA < I
REFOUT
< 10 mA,
V
REFIN
= 1.25 V
–15 15
mV
–10 mA < I
REFOUT
< 10 mA,
V
VREFIN
= 0.9 V
–15 15
–10 mA < I
REFOUT
< 10 mA,
V
REFIN
= 0.75 V
–15 15
–10 mA < I
REFOUT
< 10 mA,
V
REFIN
= 0.6 V
–15 15
I
REFOUTSRCL
REFOUT source current limit V
REFOUT
= 0 V 10 40 mA
I
REFOUTSNCL
REFOUT sink current limit V
REFOUT
= 0 V 10 40 mA
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