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TPS51116-EP

www.ti.com.cn

ZHCSAC9A –OCTOBER 2012–REVISED NOVEMBER 2012

完完整整 DDR，，DDR2，，DDR1 和和 LPDDR3 存存储储器器电电源源解解决决方方案案

同同步步降降压压控控制制器器，，1A 低低压压降降稳稳压压器器 (LDO)，，经经缓缓冲冲基基准准

查查询询样样品品: TPS51116-EP

特特性性

• 同同步步降降压压控控制制器器 (VDDQ)

应应用用范范围围

– 宽宽输输入入电电压压范范围围: 3.0V 至至 28V

• DDR/DDR2/DDR3/LPDDR3 内内存存电电源源

– 负负载载阶阶跃跃响响应应为为 100ns 的的 D−CAP™ 模模式式

• SSTL-2，，SSTL-18，，SSTL-15 和和 HSTL 终终止止

– 电电流流模模式式选选项项支支持持陶陶瓷瓷输输出出电电容容器器

支支持持国国防防、、航航空空航航天天、、和和医医疗疗应应用用

– 支支持持 S4/S5 状状态态内内的的软软关关闭闭

• 受受控控基基线线

– R

DS（（接接通通））

或或电电阻阻器器的的电电流流感感测测

• 一一个个组组装装和和测测试试场场所所

– 2.5V (DDR)，，1.8V (DDR2)，，可可调调节节至至

1.5V (DDR3) 或或 1.2V (LPDDR3) 或或

• 一一个个制制造造场场所所

0.75V 至至 3.0V 的的输输出出电电压压范范围围

• 支支持持军军用用（（-55°C 至至 125°C））温温度度范范围围

– 配配备备有有电电源源正正常常、、过过压压保保护护和和欠欠压压保保护护

• 延延长长的的产产品品生生命命周周期期

• 1A LDO (VTT)，，经经缓缓冲冲基基准准 (VREF)

• 延延长长的的产产品品变变更更通通知知

– 灌灌电电流流和和拉拉电电流流的的能能力力达达到到 1A

• 产产品品可可追追溯溯性性

– 提提供供 LDO 输输入入以以优优化化功功率率损损耗耗

– 只只需需 20μF 陶陶瓷瓷输输出出电电容容器器

– 经经缓缓冲冲的的低低噪噪声声 10mA VREF 输输出出

– 针针对对 VREF 和和 VTT 的的 ±20mV 精精度度

– 在在 S3 中中支支持持高高阻阻抗抗 (high-Z)，，在在 S4/S5 中中支支

持持软软关关闭闭

– 过过热热保保护护

说说明明

TPS51116 为 DDR/SSTL-2，DDR2/SSTL-18，DDR3/SSTL-15 和 LPDDR3 内存系统提供一个完整的电源。它集

成了一个具有 1A 灌电流/拉电流跟踪线性稳压器和经缓冲低噪声基准的同步降压控制器。 TPS51116 在空间非常

宝贵的系统中提供最低的总体解决方案成本。 TPS51116 同步控制器运行具有自适应接通时间控制的定频

400kHz，伪恒定频率脉宽调制 (PWM)，此控制可在 D-CAP™ 模式中进行配置，此模式可简化使用并实现最快瞬

态响应或者在电流模式中支持陶瓷输出电容器。 1A 灌电流/拉电流 LDO 只需 20μF (2 × 10μF) 陶瓷输出电容器即

可保持快速瞬态响应。此外，LDO 电源输入是外部可用的，这样可大大减少总体功耗。 TPS51116 支持所有睡眠

状态控制，此类控制在 S3（挂起到 RAM）中将 VTT 置于 high-Z 状态并且在 S4/S5（挂起到硬盘）中将

VDDQ，VTT 和 VTTREF（软关闭）放电。 TPS51116 具有所有保护特性，其中包括热关断并采用 20 引脚散热薄

型小外形尺寸 (HTSSOP) PowerPAD™ 封装。

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not English Data Sheet: SLUSB52

necessarily include testing of all parameters.

TPS51116-EP

ZHCSAC9A –OCTOBER 2012–REVISED NOVEMBER 2012

www.ti.com.cn

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

ORDERABLE TOP-SIDE

PACKAGE VID NUMBER

PART NUMBER MARKING

TPS51116MPWPREP V62/12602-01XE

–55°C to 125°C Plastic HTSSOP PowerPAD (PWP)

(2)

51116M

TPS51116MPWPEP V62/12602-01XE-T

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) With Cu NIPDAU lead/ball finish

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

MIN MAX UNIT

VBST –0.3 36

VBST wrt LL –0.3 6

Input voltage range V

CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET –0.3 6

PGND, VTTGND –0.3 0.3

DRVH –1.0 36

LL –1.0 30

OUT

Output voltage range V

LL, pulse width < 20 ns –5 30

COMP, DRVL, PGOOD, VTT, VTTREF –0.3 6

Operating ambient temperature range –55 150

°C

stg

Storage temperature –65 150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

THERMAL INFORMATION

TPS51116-EP

THERMAL METRIC

(1)

PWP UNITS

20 PINS

Junction-to-ambient thermal resistance

(2)

41.2

JCtop

Junction-to-case (top) thermal resistance

(3)

27.4

Junction-to-board thermal resistance

(4)

23.9

°C/W

Junction-to-top characterization parameter

(5)

1.1

Junction-to-board characterization parameter

(6)

23.7

JCbot

Junction-to-case (bottom) thermal resistance

(7)

3.6

(1) 有关传统和新的热度量的更多信息，请参阅IC

封装热度量

应用报告， SPRA953。

(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的指定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然对流条件下的结至环

境热阻。

(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI 标准 G30-

88 中能找到内容接近的说明。

(4) 按照 JESD51-8 中的说明，通过在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结板热阻。

(5) 结至顶部特征参数， ψ

，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中描述的程序从仿真数据中提取出该参

数以便获得 θ

。

(6) 结至电路板特征参数， ψ

，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中描述的程序从仿真数据中提取出该

参数以便获得 θ

。

(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得结至芯片外壳（底部）热阻。不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI

标准 G30-88 中能找到内容接近的说明。

空白

TPS51116-EP

ZHCSAC9A –OCTOBER 2012–REVISED NOVEMBER 2012

www.ti.com.cn

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V

V5IN

= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VTTREF OUTPUT

VTTREF

Output voltage, VTTREF V

VDDQSNS

/2 V

-10 mA < I

VTTREF

< 10 mA, V

VDDQSNS

= 2.5 V,

-20 20

Tolerance to V

VDDQSNS

-10 mA < I

VTTREF

< 10 mA, V

VDDQSNS

= 1.8 V,

-19 19

Tolerance to V

VDDQSNS

VTTREFTOL

Output voltage tolerance mV

-10 mA < I

VTTREF

< 10 mA, V

VDDQSNS

= 1.5 V,

-16 16

Tolerance to V

VDDQSNS

-10 mA < I

VTTREF

< 10 mA, V

VDDQSNS

= 1.2 V,

–13 13

Tolerance to V

VDDQSNS

VTTREFSRC

Source current V

VDDQSNS

= 2.5 V, V

VTTREF

= 0 V -19 -40 -83.5

VTTREFSNK

Sink current V

VDDQSNS

= 2.5 V, V

VTTREF

= 2.5 V 19 40 83.5

VDDQ OUTPUT

= 25°C, V

VDDQSET

= 0 V, No load 2.465 2.500 2.535

-55°C ≤ T

≤ 125°C, V

VDDQSET

= 0 V, No load 2.43 2.50 2.56

VDDQ

Output voltage, VDDQ T

= 25°C, V

VDDQSET

= 5 V, No load 1.776 1.800 1.830 V

-55°C ≤ T

≤ 125°C, V

VDDQSET

= 5 V, No load 1.762 1.800 1.838

-55°C ≤ T

≤ 125°C, Adjustable mode, No load 0.75 3.0

= 25°C, Adjustable mode 742.5 750 760.5

VDDQSET

VDDQSET regulation voltage mV

-55°C ≤ T

≤ 125°C, Adjustable mode 737 750 763

VDDQSET

= 0 V 215 kΩ

VDDQSNS

Input impedance, VDDQSNS V

VDDQSET

= 5 V 180

Adjustable mode 460

VDDQSET

= 0.78 V, COMP = Open -0.04

VDDQSET

Input current, VDDQSET μA

VDDQSET

= 0.78 V, COMP = 5 V -0.06

= V

= 0 V, V

VDDQSNS

= 0.5 V,

VDDQDisch

Discharge current, VDDQ 10 40 mA

MODE

= 0 V

= V

= 0 V, V

VDDQSNS

= 0.5 V,

VLDOINDisch

Discharge current, VLDOIN 700 mA

MODE

= 0.5 V

VTT OUTPUT

= V

= 5 V, V

VLDOIN

= V

VDDQSNS

= 2.5 V 1.25

VTTSNS

Output voltage, VTT V

= V

= 5 V, V

VLDOIN

= V

VDDQSNS

= 1.8 V 0.9 V

= V

= 5 V, V

VLDOIN

= V

VDDQSNS

= 1.5 V 0.75

VDDQSNS

= V

VLDOIN

= 2.5 V, V

= V

= 5 V,

-21 21

VTT

= 0 A

VTT output voltage tolerance V

VDDQSNS

= V

VLDOIN

= 2.5 V, V

= V

= 5 V,

VTTTOL25

-31 31 mV

to VTTREF |I

VTT

| < 1.5 A

VDDQSNS

= V

VLDOIN

= 2.5 V, V

= V

= 5 V,

-41 41

VTT

| < 3 A

VDDQSNS

= V

VLDOIN

= 1.8 V, V

= V

= 5 V,

-21 21

VTT

= 0 A

VTT output voltage tolerance V

VDDQSNS

= V

VLDOIN

= 1.8 V, V

= V

= 5 V,

VTTTOL18

-31 31 mV

to VTTREF |I

VTT

| < 1 A

VDDQSNS

= V

VLDOIN

= 1.8 V, V

= V

= 5 V,

-41 41

VTT

| < 2 A

VDDQSNS

= V

VLDOIN

= 1.5 V, V

= V

= 5 V,

-21 21

VTT

= 0 A

VTT output voltage tolerance V

VDDQSNS

= V

VLDOIN

= 1.5 V, V

= V

= 5 V,

VTTTOL15

-31 31 mV

to VTTREF |I

VTT

| < 1 A

VDDQSNS

= V

VLDOIN

= 1.5 V, V

= V

= 5 V,

-41 41

VTT

| < 2 A

TPS51116-EP

www.ti.com.cn

ZHCSAC9A –OCTOBER 2012–REVISED NOVEMBER 2012

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V

V5IN

= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VDDQSNS

= V

VLDOIN

= 1.2 V, V

= V

= 5 V,

-21 21

VTT

= 0 A

VTT output voltage tolerance V

VDDQSNS

= V

VLDOIN

= 1.2 V, V

= V

= 5 V,

VTTTOL12

-31 31 mV

to VTTREF |I

VTT

| < 1 A

VDDQSNS

= V

VLDOIN

= 1.2 V, V

= V

= 5 V,

-41 41

VTT

| < 1.5 A

VLDOIN

= V

VDDQSNS

= 2.5 V,

2.7 3.8 6.2

VTT

= V

VTTSNS

= 1.19 V, PGOOD = HI

VTTTOCLSRC

Source current limit, VTT

VLDOIN

= V

VDDQSNS

= 2.5 V, V

VTT

= 0 V 1.4 2.2 3.2

VLDOIN

= V

VDDQSNS

= 2.5 V,

2.65 3.6 6

VTT

= V

VTTSNS

= 1.31 V, PGOOD = HI

VTTTOCLSNK

Sink current limit, VTT

VLDOIN

= V

VDDQSNS

= 2.5 V, V

VTT

= V

VDDQ

1.4 2.2 3

VTTLK

Leakage current, VTT V

= 0 V, V

= 5 V, V

VTT

= V

VDDQSNS

/2 -11 11

VTTBIAS

Input bias current, VTTSNS V

= 5 V, V

VTTSNS

= V

VDDQSNS

/2 -1.1 1.1 μA

VTTSNSLK

Leakage current, VTTSNS V

= 0 V, V

= 5 V, V

VTT

= V

VDDQSNS

/2 -1 1

VTTDisch

Discharge current, VTT V

= V

VDDQSNS

= 0 V, V

VTT

= 0.5 V 9.5 17 mA

TRANSCONDUCTANCE AMPLIFIER

gm Gain 232 300 364 μS

= 0 V, V

= 5 V, V

VDDQSET

= 0 V,

COMPSNK

COMP maximum sink current 13

VDDQSNS

= 2.7 V, V

COMP

= 1.28 V

μA

COMP maximum source V

= 0 V, V

= 5 V, V

VDDQSET

= 0 V,

COMPSRC

-13

current V

VDDQSNS

= 2.3 V, V

COMP

= 1.28 V

= 0 V, V

= 5 V, V

VDDQSET

= 0 V,

COMPHI

COMP high clamp voltage 1.3 1.34 1.38

VDDQSNS

= 2.3 V, V

= 0 V

= 0 V, V

= 5 V, V

VDDQSET

= 0 V,

COMPLO

COMP low clamp voltage 1.17 1.21 1.25

VDDQSNS

= 2.7 V, V

= 0 V

DUTY CONTROL

Operating on-time V

= 12 V, V

VDDQSET

= 0 V 520

ON0

Startup on-time V

= 12 V, V

VDDQSNS

= 0 V 125

ON(min)

Minimum on-time T

= 25°C 100

OFF(min)

Minimum off-time T

= 25°C 350

ZERO CURRENT COMPARATOR

Zero current comparator

-6 0 6 mV

offset

OUTPUT DRIVERS

Source, I

DRVH

= –100 mA 3 6

DRVH

DRVH resistance

Sink, I

DRVH

= 100 mA 0.9 3

Ω

Source, I

DRVL

= –100 mA 3 6

DRVL

DRVL resistance

Sink, I

DRVL

= 100 mA 0.9 3

LL-low to DRVL-on 10

Dead time ns

DRVL-off to DRVH-on 20

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