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TPS23882B是一款由德州仪器（TI）推出的专为PoE（Power over Ethernet）Type-3 2对线应用设计的8通道PSE（Power Sourcing Equipment）控制器。这款控制器遵循IEEE 802.3bt标准，旨在在以太网电缆上供电，同时能检测并连接具有有效签名的受电设备（PD），完成互相识别，并提供电力。该控制器的核心特性包括： 1. **自适应模式**：用户可以选择15-W或30-W的无MCU需求的自主模式，简化系统设计。 2. **高精度电流感应**：每个端口配备一个14位集成电流ADC，提供2%的电流感应精度，确保了在DC断开时的噪声免疫力。 3. **电源限制可编程性**：允许±4%的功率限制精度调整，可根据实际需求设定。 4. **多级端口功率分配**：支持4 W、7 W、15.4 W和30 W四种端口功率分配，灵活满足不同应用。 5. **快速端口关闭输入**：1-或3位的快速端口关闭输入，便于快速响应异常情况。 6. **自动分类发现与功率测量**：自动识别PD设备类型并进行功率测量，提升系统效率。 7. **四点检测技术**：采用“Never Fooled”四点检测技术，提高系统稳定性，防止误操作。 8. **过冲和工作折叠保护**：保护系统免受大电流冲击和运行期间的故障。 9. **端口重映射功能**：允许在必要时重新配置端口功能。 10. **I2C通信**：支持8位或16位I2C通信协议，便于与系统其他组件的交互。 11. **处理器控制的操作模式**：提供自动、半自动和手动/诊断模式，以适应各种工作场景。 12. **端口电压监控和遥测**：实时监测每个端口的电压，确保系统的稳定运行。 13. **工作温度范围**：可在-40°C到+125°C的温度范围内正常工作。此外，通过SRAM编程功能，用户可以在现场通过I2C接口进行固件升级，以保持与最新IEEE标准的兼容性和与PoE设备的互操作性。这使得TPS23882B不仅适用于视频录像机（如NVR、DVR）、小型企业交换机，还适用于校园和分支交换机等应用场景。总的来说，TPS23882B以其高精度、灵活性和智能管理特性，成为实现高效PoE解决方案的理想选择。

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TPS23882B Type-3 2-Pair 8-Channel PSE Controller with Autonomous Mode, SRAM,

and 200-mΩ RSENSE

1 Features

• IEEE 802.3bt PSE solution for PoE 2 Type-3 2-Pair

power over ethernet applications

• Compatible with TI's FirmPSE system firmware

• SRAM Programmable memory

• Programmable power limiting accuracy ±4%

• 200-mΩ Current sense resistor

• User selectable 15-W or 30-W autonomous mode

with no MCU required

• Selectable 2-pair port power allocations

– 4 W, 7 W, 15.4 W, or 30 W

• Dedicated 14-bit integrating current ADC per port

– Noise immune MPS for DC disconnect

– 2% Current sensing accuracy

• 1- or 3-bit fast port shutdown input

• Auto-class discovery and power measurement

• Never Fooled 4-point detection

• Inrush and operational foldback protection

• 425-mA and 1.25-A selectable current limits

• Port re-mapping

• 8-bit or 16-bit I

C communication

• Flexible processor controlled operating modes

– Auto, semi auto and manual / diagnostic

• Per port voltage monitoring and telemetry

• –40°C to +125°C temperature operation

2 Applications

• Video recorder (NVR, DVR, and so forth)

• Small business switch

• Campus and branch switches

3 Description

The TPS23882B is an 8-channel power sourcing

equipment (PSE) controller engineered to insert

power onto Ethernet cables in accordance with the

IEEE 802.3bt standard. The PSE controller can detect

powered devices (PDs) that have a valid signature,

complete mutual identification, and apply power.

The TPS23882B improves on the TPS2388

with reduced current sense resistors, SRAM

programmability, programmable power limiting,

capacitance measurement, and compatibility with TI's

FirmPSE system firmware (see Device Comparison

Table).

Programmable SRAM enables in-field firmware

upgradability over I

C to ensure IEEE compliance and

interoperability with the latest PoE enabled devices.

Dedicated per port ADCs provide continuous port

current monitoring and the ability to perform parallel

classification measurements for faster port turn on

times. A 1.25-A port current limit and adjustable

power limiting allows for the support of non-standard

applications above 60-W sourced. The 200-mΩ

current sense resistor and external FET architecture

allow designs to balance size, efficiency, thermal and

solution cost requirements.

Port remapping and pin-to-pin compatibility with

the TPS2388, TPS23880, and TPS23881 devices

eases migration from previous generation PSE

designs and enables interchangeable 2-layer PCB

designs to accommodate different system PoE power

configurations.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS23882B VQFN (56) 8.00 mm × 8.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

VPWR

TPS23882

+54V

2P Port #5

0.1uF

100V

0.1uF

100V

2P Port #6

SEN6

GAT6

DRAIN6

KSENSEC

0.200:

SEN5

GAT5

DRAIN5

0.200:

VDD

+3.3V

SEN2

GAT2

DRAIN2

KSENSEA

SEN1

GAT1

DRAIN1

Note: Only four channels shown

Alt A RJ45 & XFrmr

2P Port #7

2P Port #8

Alt A RJ45 & XFrmr

SCL

INT

SDAO

SDAI

I2C Bus

2P Port #1

0.1uF

100V

0.1uF

100V

2P Port #2

0.200:

Alt A

RJ45 & XFrmr

Alt ARJ45 & XFrmr

2P Port #3

2P Port #4

Alt ARJ45 & XFrmr

GND

Simplified Schematic

www.ti.com

TPS23882B

SLVSG51 – APRIL 2021

Submit Document Feedback

Product Folder Links: TPS23882B

TPS23882B

SLVSG51 – APRIL 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table............................................... 3

6 Pin Configuration and Functions...................................4

6.1 Detailed Pin Description..............................................5

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 ESD Ratings............................................................... 7

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................8

7.6 Typical Characteristics.............................................. 14

8 Parameter Measurement Information.......................... 19

8.1 Timing Diagrams....................................................... 19

9 Detailed Description......................................................21

9.1 Overview................................................................... 21

9.2 Functional Block Diagram......................................... 26

9.3 Feature Description...................................................27

9.4 Device Functional Modes..........................................29

9.5 I

C Programming...................................................... 30

9.6 Register Maps...........................................................33

10 Application and Implementation.............................. 106

10.1 Application Information......................................... 106

10.2 Typical Application................................................ 109

11 Power Supply Recommendations............................ 115

11.1 VDD....................................................................... 115

11.2 VPWR....................................................................115

12 Layout......................................................................... 116

12.1 Layout Guidelines................................................. 116

12.2 Layout Example.................................................... 117

13 Device and Documentation Support........................118

13.1 Documentation Support........................................ 118

13.2 Receiving Notification of Documentation Updates 118

13.3 Support Resources............................................... 118

13.4 Trademarks........................................................... 118

13.5 Electrostatic Discharge Caution............................ 118

13.6 Glossary................................................................ 118

14 Mechanical, Packaging, and Orderable

Information.................................................................. 118

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE REVISION NOTES

April 2021 * Initial Release

TPS23882B

SLVSG51 – APRIL 2021

www.ti.com

2 Submit Document Feedback

Product Folder Links: TPS23882B

Table 6-1. Pin Functions (continued)

I/O DESCRIPTION

NAME NO.

15, 16, 18, 19 O

No connect pins. These pins are internally biased at 1/3 and 2/3 of VPWR in order to control the voltage

gradient from VPWR. Leave open.

22, 27, 28 — No connect pin. Leave open.

OSS 56 I Channel 1-8 fast shutdown. This pin is internally pulled down to DGND.

RESET 44 I Reset input. When asserted low, the TPS23882B is reset. This pin is internally pulled up to VDD.

SCL 53 I Serial clock input for I

C bus.

SDAI 54 I Serial data input for I

C bus. This pin can be connected to SDAO for non-isolated systems.

SDAO 55 O

Serial data output for I

C bus. This pin can be connected to SDAI for non-isolated systems. This output is

open-drain.

AUTO 52 I/O Autonomous mode enable and selection pin.

SEN1-8

2, 6, 9, 13, 30, 34,

37, 41

I Channel 1-8 current sense input.

TEST0-5

20, 23, 24, 25, 26,

I/O Used internally for test purposes only. Leave open.

Thermal pad — — The DGND and AGND terminals must be connected to the exposed thermal pad for proper operation.

VDD 43 — Digital supply. Bypass with 0.1 µF to DGND pin.

VPWR 17 — Analog 54-V positive supply. Bypass with 0.1 µF to AGND pin.

6.1 Detailed Pin Description

The following descriptions refer to the pinout and the functional block diagram.

DRAIN1-DRAIN8: Channels 1-8 output voltage monitor and detect sense. Used to measure the port output

voltage, for port voltage monitoring, port power good detection and foldback action. Detection probe currents

also flow into this pin.

The TPS23882B uses an innovative 4-point technique to provide reliable PD detection and avoids powering an

invalid load. The discovery is performed by sinking two different current levels via the DRAINn pin, while the PD

voltage is measured from VPWR to DRAINn. If prior to starting a new detection cycle the port voltage is >2.5 V,

an internal 100-kΩ resistor is connected in parallel with the port and a 400-ms detect backoff period is applied to

allow the port capacitor to be discharged before the detection cycle starts.

There is an internal resistor between each DRAINn pin and VPWR in any operating mode except during

detection or while the port is ON. If the port n is not used, DRAINn can be left floating or tied to GND.

GAT1-GAT8: Channels 1-8 gate drive outputs are used for external N-channel MOSFET gate control. At port

turn on, it is driven positive by a low current source to turn the MOSFET on. GATn is pulled low whenever any of

the input supplies are low or if an overcurrent timeout has occurred. GATn is also pulled low if the port is turned

off by use of manual shutdown inputs. Leave floating if unused.

For improved design robustness, the current foldback functions limit the power dissipation of the MOSFET

during low resistance load or short-circuit events and during the inrush period at port turn on. There is also fast

overload protection comparator for major faults like a direct short that forces the MOSFET to turn off in less than

a microsecond.

The circuit leakage paths between the GATn pin and any nearby DRAINn pin, GND or Kelvin point connection

must be minimized (< 250 nA), to ensure correct MOSFET control.

INT: This interrupt output pin asserts low when a bit in the interrupt register is asserted. This output is open-

drain.

KSENSA, KSENSB, KSENSC, KSENSD: Kelvin point connection used to perform a differential voltage

measurement across the associated current sense resistors.

Each KSENS is shared between two neighbor SEN pins as following: KSENSA with SEN1 and SEN2, KSENSB

with SEN3 and SEN4, KSENSC with SEN5 and SEN6, KSENSD with SEN7 and SEN8. To optimize the

measurement accuracy, ensure proper PCB layout practices are followed.

www.ti.com

TPS23882B

SLVSG51 – APRIL 2021

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