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Core Scalar

Chip

D3-

GND

D3+

D2-

GND

D2+

D1-

GND

D1+

D0-

GND

D0+

HTP_D

5 V

GND

D_DAT

D_CLK

CE_R

5 V 5 V 3.3 V

0.1 uF

5 V

100 kW

47 kW

1 kW

27 kW

10 kW

HPD_IN

DDAT_IN

DCLK_IN

CEC_IN

HPD_OUT

DDAT_OUT

DCLK_OUT

CEC_OUT

LV_SUPPLY

5V_SUPPLY

ESD_BYP

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

TPD12S520

SLVS640F –OCTOBER 2007–REVISED FEBRUARY 2015

TPD12S520 Single-Chip HDMI Receiver Port Protection and Interface Device

1 Features 3 Description

The TPD12S520 is a single-chip electro-static

• IEC 61000-4-2 Level 4 ESD Protection

discharge (ESD) circuit protection device for the high-

– ±8-kV Contact Discharge on External Lines

definition multimedia interface (HDMI) receiver port.

• Single-Chip ESD Solution for HDMI Driver

While providing ESD protection with transient voltage

suppression (TVS) diodes, the TVS protection adds

• 12 Channel ESD Protection Diodes

little or no additional glitch in the high-speed

• Supports All HDMI 1.3 and HDMI 1.4b Data Rates

differential signals. The high-speed transition

(–3 dB Frequency > 3 GHz)

minimized differential signaling (TMDS) ESD

• 0.8-pF Capacitance for the High Speed TMDS

protection lines add only 0.8-pF capacitance.

Lines

The low-speed control lines offer voltage-level shifting

• 0.05-pF Matching Capacitance Between the

to eliminate the need for an external voltage level-

Differential Signal Pair

shifter IC. The control line TVS diodes add 3.5-pF

capacitance to the control lines. The 38-pin DBT

• 38-Pin TSSOP Provides Seamless Layout Option

package offers a seamless layout routing option to

with HDMI Connector

eliminate the routing glitch for the differential signal

• 24-Pin WQFN Package for Space Constrained

pairs. The DBT package pitch (0.5 mm) matches with

Applications

the HDMI connector pitch. In addition, the pin

• Backdrive Protection

mapping follows the same order as the HDMI

connector pin mapping. This HDMI receiver port

• Lead-Free Package

protection and interface device is designed

specifically for HDMI receiver-interface protection.

2 Applications

The 24-pin RMN package offers flow through routing

• Video Interface

using only two layers for highly integrated, space-

efficient full HDMI protection.

• Consumer Electronics

• Displays and Digital Televisions

Device Information

(1)

• Handheld Displays

DEVICE NAME PACKAGE BODY SIZE (NOM)

TSSOP (38) 6.40 mm × 9.70 mm

TPD12S520

WQFN (24) 4.50 mm × 1.50 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Circuit Protection Scheme

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPD12S520

SLVS640F –OCTOBER 2007–REVISED FEBRUARY 2015

www.ti.com

Table of Contents

7.3 Feature Description................................................... 8

1 Features.................................................................. 1

7.4 Device Functional Modes.......................................... 8

2 Applications ........................................................... 1

8 Application and Implementation .......................... 9

3 Description ............................................................. 1

8.1 Application Information.............................................. 9

4 Revision History..................................................... 2

8.2 Typical Application ................................................... 9

5 Pin Configuration and Functions......................... 3

9 Power Supply Recommendations...................... 10

6 Specifications......................................................... 4

10 Layout................................................................... 11

6.1 Absolute Maximum Ratings ...................................... 4

10.1 Layout Guidelines ................................................. 11

6.2 ESD Ratings ............................................................ 4

10.2 Layout Example .................................................... 11

6.3 Recommended Operating Conditions....................... 4

11 Device and Documentation Support ................. 12

6.4 Thermal Information.................................................. 5

11.1 Trademarks........................................................... 12

6.5 Electrical Characteristics........................................... 5

11.2 Electrostatic Discharge Caution............................ 12

6.6 Typical Characteristics.............................................. 6

11.3 Glossary................................................................ 12

7 Detailed Description .............................................. 7

12 Mechanical, Packaging, and Orderable

7.1 Overview ................................................................... 7

Information ........................................................... 12

7.2 Functional Block Diagram ......................................... 7

4 Revision History

Changes from Revision E (September 2014) to Revision F Page

• Added clarification to HDMI data rates................................................................................................................................... 1

• Added clarification to HDMI data rates................................................................................................................................... 8

Changes from Revision D (December 2013) to Revision E Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device

Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout

section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

section ................................................................................................................................................................................... 1

Changes from Revision C (April 2009) to Revision D Page

• Added new application to Applications section. .................................................................................................................... 1

• Added RMN Package to Datasheet. ..................................................................................................................................... 1

• Updated RMN Package. ........................................................................................................................................................ 1

• Updated Pin Description Table. ............................................................................................................................................. 4

• Added additonal graphs to Typical Performance section. ..................................................................................................... 6

Product Folder Links: TPD12S520

TPD12S520

www.ti.com

SLVS640F –OCTOBER 2007–REVISED FEBRUARY 2015

5 Pin Configuration and Functions

Pin Functions

PIN NO.

ESD

NAME TYPE DESCRIPTION

LEVEL

DBT RMN

5V_SUPPLY 1 12 PWR 2 kV

(1)

Bias for TMDS protection

LV_SUPPLY 2 13 PWR 2 kV

(1)

Bias for CE/DDC/HOTPLUG level shifters

3, 5, 8, 11,14,

6, 9, 10,

GND, TMDS_GND 25, 28, 31, 34, GND NA TMDS ESD and parasitic GND return

(2)

14, 17

TMDS_D2+ 4, 35 18 IO 8 kV

(3)

TMDS 0.8-pF ESD protection

(4)

TMDS_D2– 6, 33 19 IO 8 kV

(3)

TMDS 0.8-pF ESD protection

(4)

TMDS_D1+ 7, 32 15 IO 8 kV

(3)

TMDS 0.8-pF ESD protection

(4)

TMDS_D1– 9, 30 16 IO 8 kV

(3)

TMDS 0.8-pF ESD protection

(4)

TMDS_D0+ 10, 29 8 IO 8 kV

(3)

TMDS 0.8-pF ESD protection

(4)

TMDS_D0– 12, 27 7 IO 8 kV

(3)

TMDS 0.8-pF ESD protection

(4)

TMDS_CK+ 13, 26 5 IO 8 kV

(3)

TMDS 0.8-pF ESD protection

(4)

TMDS_CK– 15, 24 4 IO 8 kV

(3)

TMDS 0.8-pF ESD protection

(4)

CE_REMOTE_IN 16 20 IO 2 kV

(1)

LV_SUPPLY referenced logic level into ASIC

DDC_CLK_IN 17 21 IO 2 kV

(1)

LV_SUPPLY referenced logic level into ASIC

DDC_DAT_IN 18 22 IO 2 kV

(1)

LV_SUPPLY referenced logic level into ASIC

HOTPLUG_DET_IN 19 23 IO 2 kV

(1)

LV_SUPPLY referenced logic level into ASIC

5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD

(5)

HOTPLUG_DET_OUT 20 24 IO 8 kV

(3)

connector

(1) Human body model (HBM) per MIL-STD-883, Method 3015, C

DISCHARGE

= 100 pF, R

DISCHARGE

= 1.5 kΩ, 5V_SUPPLY and LV_SUPPLY

within recommended operating conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with

a 0.1-μF ceramic capacitor connected to GND.

(2) These pins should be routed directly to the associated GND pins on the HDMI connector, with single-point ground vias at the connector.

(3) Standard IEC 61000-4-2, C

DISCHARGE

= 150 pF, R

DISCHARGE

= 330 Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating

conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-μF ceramic capacitor

connected to GND.

(4) These two pins must be connected together inline on the PCB.

(5) This output can be connected to an external 0.1-μF ceramic capacitor, resulting in an increased ESD withstand voltage rating.

Product Folder Links: TPD12S520

TPD12S520

SLVS640F –OCTOBER 2007–REVISED FEBRUARY 2015

www.ti.com

Pin Functions (continued)

PIN NO.

ESD

NAME TYPE DESCRIPTION

LEVEL

DBT RMN

5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to

DDC_DAT_OUT 21 1 IO 8 kV

(3)

connector

5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to

DDC_CLK_OUT 22 2 IO 8 kV

(3)

connector

5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to

CE_REMOTE_OUT 23 3 IO 8 kV

(3)

connector

ESD bypass. This pin must be connected to a 0.1-μF ceramic

ESD_BYP 37 11 IO 2 kV

(1)

capacitor.

NC 38 NA No connection

6 Specifications

6.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

5V_SUPPLY

Supply voltage –0.3 6 V

LV_SUPPLY

I/O

DC voltage at any channel input –0.5 6 V

Operating Free Air Temperature –40 85 °C

stg

Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per MIL-STD-

See Pin Configuration

883, Method 3015, C

DISCHARGE

= 100 pF, ±2000

and Functions

DISCHARGE

= 1.5 kΩ

(1)

(ESD)

Electrostatic discharge V

See Pin Configuration

IEC 61000-4-2 Contact Discharge

(2)

±8000

and Functions

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

Operating free-air temperature –40 85 °C

5V_SUPPLY Operating supply voltage GND 5 5.5 V

LV_SUPPLY Bias supply voltage 1 3.3 5.5 V

Product Folder Links: TPD12S520

TPD12S520

www.ti.com

SLVS640F –OCTOBER 2007–REVISED FEBRUARY 2015

6.4 Thermal Information

TPD12S520

THERMAL METRIC

(1)

DBT RMN UNIT

38 PINS 24 PINS

θJA

Junction-to-ambient thermal resistance 83.6 80.8

θJC(top)

Junction-to-case (top) thermal resistance 29.8 36.4

θJB

Junction-to-board thermal resistance 44.7 27.1 °C/W

Junction-to-top characterization parameter 2.9 1.4

Junction-to-board characterization parameter 44.1 27.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Operating supply current 5V_SUPPLY = 5 V 1 5 µA

Bias supply current LV_SUPPLY = 3.3 V 1 2 mA

OFF-state leakage

OFF

current, level-shifting LV_SUPPLY = 0 V 0.1 1 µA

NFET

TMDS_D[2:0]+/–,

TMDS_CK+/–,

Current conducted from

CE_REMOTE_OUT,

output pins to

BACK DRIVE

5V_SUPPLY < V

CH_OUT

0.1 5 µA

V_SUPPLY rails when

DDC_DAT_OUT,

powered down

DDC_CLK_OUT,

HOTPLUG_DET_OUT

Voltage drop across

level-shifting NFET when LV_SUPPLY = 2.5 V, V

= GND, I

= 3 mA 75 95 140 mV

= 8 mA, Top diode 1

Diode forward voltage V

= 25°C

(1)

Bottom diode 1

Positive transients 9

Channel clamp voltage at

TA = 25°C

(1)(2)

±8 kV HBM ESD

Negative transients -9

Positive transients 0.6

DYN

Dynamic resistance I = 1 A, T

= 25°C

(3)

Negative transients 0.5

TMDS channel leakage

= 25°C

(1)

0.01 1 µA

LEAK

current

, 5V_SUPPLY= 5 V, Measured at 1 MHz,

TMDS channel input

0.8 1.0 pF

capacitance

TMDS V

BIAS

= 2.5 V

(1)

ΔC

, 5V_SUPPLY= 5 V, Measured at 1 MHz,

TMDS channel input

0.05 pF

capacitance matching

TMDS V

BIAS

= 2.5 V

(1)(4)

Mutual capacitance

5V_SUPPLY= 0 V, Measured at 1 MHz,

MUTUAL

between signal pin and 0.07 pF

BIAS

= 2.5 V

(1)

adjacent signal pin

DDC 3.5 4

Level-shifting input

5V_SUPPLY= 0 V, Measured at 100 KHz,

capacitance, capacitance CEC 3.5 4 pF

BIAS

= 2.5 V

(1)

to GND

HP 3.5 4

(1) This parameter is specified by design and verified by device characterization

(2) Human-Body Model (HBM) per MIL-STD-883, Method 3015, C

DISCHARGE

= 100 pF, R

DISCHARGE

= 1.5 kΩ

(3) These measurements performed with no external capacitor on ESD_BYP.

(4) Intrapair matching, each TMDS pair (i.e., D+, D–)

Product Folder Links: TPD12S520

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