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TI-UCD8220.pdf
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCD8220
SLUS652E –MARCH 2005–REVISED APRIL 2020
UCD8220 Digitally Managed Push-Pull Analog PWM Controllers
1
1 Features
1
• For digitally managed power supplies using μCs
or the TMS320 ™ DSP family
• Voltage or peak current mode control with cycle-
by-cycle current limiting
• Clock input from digital controller to set operating
frequency and max duty cycle
• Analog PWM comparator
• 2-MHz switching frequency
• 110-V input startup circuit and thermal shutdown
(UCD8620)
• Internal programmable slope compensation
• 3.3-V, 10-mA linear regulator
• DSP/μC compatible inputs
• Dual ±4-A TrueDrive™ integrated circuit high
current drivers
• 10-ns typical rise and fall times with 2.2-nF
• 25-ns input-to-output propagation delay
• 25-ns current sense-to-output propagation delay
• Programmable current-limit threshold
• Digital output current-limit flag
• 4.5-V to 15.5-V supply voltage range
• Rated from –40°C to 105°C
2 Applications
• Digitally managed switch mode power supplies
• Push-pull, half-bridge, or full-bridge converters
• Battery chargers
3 Description
The UCD8220 analog pulse-width modulator (PWM)
device is used in digitally managed power supplies
using a microcontroller or the TMS320 DSP family.
The UCD8220 device is a double-ended PWM
controller configured with push-pull drive logic.
Systems using the UCD8220 device close the PWM
feedback loop with traditional analog methods, but
the UCD8220 controller includes circuitry to interpret
a time-domain digital pulse train. The pulse train
contains the operating frequency and maximum duty
cycle limit which are used to control the power supply
operation. The device circuitry eases implementation
of a converter with high level control features without
the added complexity or possible PWM resolution
limitations of closing the control loop in the discrete
time domain.
The UCD8220 device can be configured for either
peak current mode or voltage mode control. The
device provides a programmable current-limit function
and a digital output current-limit flag which can be
monitored by the host controller to set the current
limit operation. For fast switching speeds, the output
stage uses the TrueDrive output circuit architecture,
which delivers rated current of ±4-A into the gate of a
MOSFET. Finally the device also includes a 3.3-V,
10-mA linear regulator to provide power to the digital
controller or act as a reference in the system.
The UCD8220 controller is compatible with the
standard 3.3-V I/O ports of UCD9K digital power
controllers, DSPs, microcontrollers, or ASICs and is
offered in the PowerPAD™ integrated circuit package
HTSSOP.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
UCD8220 HTSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Figure 1. UCD8220 Typical Simplified Push-Pull
Converter Application Schematic
2
UCD8220
SLUS652E –MARCH 2005–REVISED APRIL 2020
www.ti.com
Product Folder Links: UCD8220
Submit Documentation Feedback Copyright © 2005–2020, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 17
8 Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
10.3 Thermal Considerations........................................ 24
11 Device and Documentation Support ................. 24
11.1 Documentation Support ........................................ 24
11.2 Trademarks........................................................... 24
11.3 Electrostatic Discharge Caution............................ 24
11.4 Glossary................................................................ 24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2006) to Revision E Page
• Added the following sections to the data sheet: Device Functional Modes, Application Information, Design
Requirements, Application Curves, Power Supply Recommendations, and Layout Example............................................... 1
• Changed Updated ESD table ................................................................................................................................................ 4
• Changed Junction temperature to 105 Celsius ...................................................................................................................... 5
• Changed Junction temperature to 105 Celsius ...................................................................................................................... 6
• Added Layout example for Industrial version ...................................................................................................................... 23
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
CLK
3V3
ISET
AGND
CTRL
CLF
ILIM
NC
NC
V
DD
PVDD
OUT1
OUT2
PGND
CS
3
UCD8220
www.ti.com
SLUS652E –MARCH 2005–REVISED APRIL 2020
Product Folder Links: UCD8220
Submit Documentation FeedbackCopyright © 2005–2020, Texas Instruments Incorporated
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP With PowerPAD
Top View
NC – No internal connection
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
3V3 3 O
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of
current. Place a 0.22-μF ceramic capacitor from this pin to analog ground.
AGND 5 — Analog ground return
CLF 7 O
Current-limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output
driver is forced low and the current-limit flag (CLF) is set high. The CLF signal is latched high until
the device receives the next rising edge on the CLK pin. This signal is also used for the start-up
handshaking between the digital controller and the analog controller
CLK 2 I
Clock. Input pulse train contains operating frequency and maximum duty cycle limit. This pin is a
high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. An internal
Schmitt trigger comparator isolates the internal circuitry from any external noise.
CS 9 I
Current sense pin. A fast current-limit comparator connected to the CS pin is used to protect the
power stage by implementing cycle-by-cycle current limiting.
CTRL 6 I
Input for the error feedback voltage from the external error amplifier. This input is multiplied by 0.5
and routed to the negative input of the PWM comparator
ILIM 8 I
Current-limit threshold set pin. The current-limit threshold can be set to any value between 0.25 V
and 1 V. The default value while open is 0.5 V.
ISET 4 I
Pin for programming the current used to set the amount of slope compensation in peak current-
mode control or to set the internal capacitor charging in voltage-mode control.
NC
1
— No connection.15
16
OUT1 12 O The high-current TrueDrive integrated circuit driver output.
OUT2 11 O The high-current TrueDrive integrated circuit driver output.
PGND 10 — Power ground return. This pin should be connected close to the source of the power MOSFET.
PVDD 13
— Supply pin provides power for the output drivers. This pin is not connected internally to the V
DD
supply rail. The bypass capacitor for this pin should be returned to PGND.
V
DD
14 I
Supply input pin to power the control circuitry. Bypass the pin with a capacitor with a value of at
least 4.7 μF, returned to AGND.
4
UCD8220
SLUS652E –MARCH 2005–REVISED APRIL 2020
www.ti.com
Product Folder Links: UCD8220
Submit Documentation Feedback Copyright © 2005–2020, Texas Instruments Incorporated
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
MIN MAX UNIT
Supply voltage, V
DD
16 V
Supply current, I
DD
Quiescent 20
mA
Switching, T
A
= 25°C, T
J
= 105°C, V
DD
= 12 V 200
Output gate-drive voltage, V
O
OUTx –1 PVDD V
Output gate-drive sink current, I
O(sink)
OUTx 4
A
Output gate-drive source current,
I
O(source)
OUTx –4
Analog input ISET, CS, CTRL, ILIM –0.3 3.6 V
Digital I/Os CLK, CLF –0.3 3.6
Continuous total power dissipation See Thermal Information
Operating junction temperature range, T
J
–55 150 °C
Lead temperature (Soldering, 10 sec) 300 °C
Storage temperature, T
stg
–65 150 °C
(1) Tested to JEDEC standard EIA/JESD22-A114-B specification.
6.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM)
(1)
±2000
V
Charged device model (CDM) ±500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
DD
Supply voltage, PVDD 4.5 15.5 V
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.4 Thermal Information
THERMAL METRIC
(1)
PWP (HTSSOP)
UNIT
16 PINS
R
θJA
Junction-to-ambient thermal resistance 40.1
°C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 29.5
R
θJB
Junction-to-board thermal resistance 24.2
ψ
JT
Junction-to-top characterization parameter 1
ψ
JB
Junction-to-board characterization parameter 24
R
θJC(bot)
Junction-to-case (bottom) thermal resistance 1.8
5
UCD8220
www.ti.com
SLUS652E –MARCH 2005–REVISED APRIL 2020
Product Folder Links: UCD8220
Submit Documentation FeedbackCopyright © 2005–2020, Texas Instruments Incorporated
(1) Specified by design. Not 100% tested in production.
6.5 Electrical Characteristics
V
DD
= 12 V, 4.7-µF capacitor from V
DD
to AGND, 1 μF from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND, T
A
= T
J
=
–40°C to 105°C, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY SECTION
Supply current, OFF V
DD
= 4.2 V 300 500 µA
Supply current, ON Outputs not switching, CLK = low 2 3 mA
LOW VOLTAGE UNDERVOLTAGE LOCKOUT
V
DD
UVLO ON 4.25 4.5 4.75 V
V
DD
UVLO OFF 4.05 4.25 4.45 V
V
DD
UVLO hysteresis 150 250 350 mV
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point T
A
= 25°C, I
LOAD
= 0 3.267 3.3 3.333 V
3V3 set point over temperature 3.234 3.3 3.366 V
3V3 load regulation I
LOAD
= 1 mA to 10 mA, VDD = 5 V 1 6.6 mV
3V3 line regulation V
DD
= 4.75 V to 12 V, I
LOAD
= 10 mA 1 6.6 mV
Short circuit current V
DD
= 4.75 to 12 V 11 20 35 mA
3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1 V
3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9 V
CLOCK INPUT (CLK)
VIT+
HIGH, positive-going input
threshold voltage
1.65 2.08 V
VIT–
LOW negative-going input
threshold voltage
1.16 1.5 V
(VIT+) –
(VIT–)
Input voltage hysteresis 0.6 0.8 V
Frequency OUTx = 1 MHz 2 MHz
SLOPE COMPENSATION (ISET)
ISET Voltage V
ISET
, 3V3 = 3.3 V, ±2% 1.78 1.84 1.90 V
m V
SLOPE
(I-Mode)
R
ISET
= 6.19 kΩ to AGND, CS = 0.25 V,
CTRL = 2.5 V
1.48 2.12 2.76
V/µs
R
ISET
= 100 kΩ to AGND, CS = 0.25 V,
CTRL = 2.5 V
0.099 0.142 0.185
R
ISET
= 499 kΩ to AGND, CS = 0.25 V,
CTRL = 2.5 V
0.019 0.028 0.037
m V
SLOPE
(V-Mode)
R
ISET
= 4.99 kΩ to 3V3, CTRL = 2.5 V 1.44 2.06 2.68
V/µsR
ISET
= 100 kΩ to 3V3, CTRL = 2.5 V 0.079 0.114 0.148
R
ISET
= 402 kΩ to 3v3, CTRL = 2.5 V 0.019 0.027 0.035
ISET resistor range
Current mode control; R
ISET
connected to
AGND
6.19 499 kΩ
ISET resistor range
Voltage mode control; R
ISET
connected to
3V3
4.99 402 kΩ
ISET current range
Voltage mode control with Feed-Forward;
R
ISET
connected to VIN
3.7 300 μA
PWM
PWM offset at CTRL input 3V3 = 3.3 V ±2% 0.45 0.51 0.6 V
CTRL buffer gain
(1)
Gain from CTRL to PWM comparator input 0.5 V/V
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