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TI-UC1854.pdf
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16
3
4
ISENSE
5
2
PKLMT
14
13
12 1
9
VREF
VREF
VREF
RSETSSCT
15
VCC
VCC
11
7
VSENSE
8
6
10
VREF
VCC
ENA
IAC
VRMS
EMI
Filter
Line
Input
UC3854
VOUT
400 VDC
MULTOUT CAOUT
GTDRV
VAOUT
GND
Copyright © 2016, Texas Instruments Incorporated
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UC1854
,
UC2854
,
UC3854
SLUS336A –JUNE 1998–REVISED DECEMBER 2016
UCx854 High-Power Factor Preregulator
1
1 Features
1
• Control Boost PWM to 0.99 Power Factor
• Limit Line-Current Distortion to < 5%
• World-Wide Operation Without Switches
• Feedforward Line Regulation
• Average Current-Mode Control
• Low Noise Sensitivity
• Low Startup Supply Current
• Fixed-Frequency PWM Drive
• Low-Offset Analog Multiplier and Divider
• 1-A Totem-Pole Gate Driver
• Precision Voltage Reference
2 Applications
• Offline AC-to-DC Converters
• Medical, Industrial, Telecom, and IT Power
Supplies
• Uninterruptible Power Supplies (UPS)
• Appliances and White Goods
3 Description
The UC1854 provides active-power factor correction
for power systems that otherwise would draw non-
sinusoidal current from sinusoidal power lines. This
device implements all the control functions necessary
to build a power supply capable of optimally using
available power-line current while minimizing line-
current distortion. To do this, the UC1854 contains a
voltage amplifier, an analog multiplier and divider, a
current amplifier, and a fixed-frequency PWM.
In addition, the UC1854 contains a power MOSFET-
compatible gate driver, 7.5-V reference, line
anticipator, load-enable comparator, low-supply
detector, and overcurrent comparator.
The UC1854 uses average current-mode control to
accomplish fixed-frequency current control with
stability and low distortion. Unlike peak current-mode,
average current control accurately maintains
sinusoidal line current without slope compensation
and with minimal response to noise transients.
The high reference voltage and high oscillator
amplitude of the UC1854 minimize noise sensitivity
while fast PWM elements permit chopping
frequencies above 200 kHz. The UC1854 is used in
single-phase and three-phase systems with line
voltages that vary from 75 V to 275 V and line
frequencies across the 50-Hz to 400-Hz range. To
reduce the burden on the circuitry that supplies power
to this device, the UC1854 features low starting
supply current.
These devices are available packaged in 16-pin
plastic and ceramic dual in-line packages, and a
variety of surface-mount packages.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
UC1854, UC2854,
UC3854
SOIC (16) 7.50 mm × 10.30 mm
PLCC (20) 8.96 mm × 8.96 mm
CDIP (16) 6.92 mm × 19.56 mm
PDIP (16) 6.35 mm × 19.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
2
UC1854
,
UC2854
,
UC3854
SLUS336A –JUNE 1998–REVISED DECEMBER 2016
www.ti.com
Product Folder Links: UC1854 UC2854 UC3854
Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Typical Characteristics.............................................. 8
8 Detailed Description............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1 Documentation Support ........................................ 18
12.2 Related Links ........................................................ 18
12.3 Receiving Notification of Documentation Updates 18
12.4 Community Resources.......................................... 18
12.5 Trademarks........................................................... 18
12.6 Electrostatic Discharge Caution............................ 18
12.7 Glossary................................................................ 18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 1998) to Revision A Page
• Added Applications section, Device Information table, Pin Configuration and Functions section, Specifications
section, ESD Ratings table, Recommended Operating Conditions table, Detailed Description section, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
• Added Thermal Information table ........................................................................................................................................... 6
• Changed IAC value in both Multiplier Output vs Multiplier Inputs images from mA to µA. ................................................... 8
4CAOUT
5ISENSE
6NC
7MULTOUT
8IAC
9VAOUT
10VRMS
11NC
12VREF
13ENA
14 VSENSE
15 RSET
16 NC
17 SS
18 CT
19 VCC
20 GTDRV
1 NC
2 GND
3 PKLMT
Not to scale
1GND 16 GTDRV
2PKLMT 15 VCC
3CAOUT 14 CT
4ISENSE 13 SS
5MULTOUT 12 RSET
6IAC 11 VSENSE
7VAOUT 10 ENA
8VRMS 9 VREF
Not to scale
3
UC1854
,
UC2854
,
UC3854
www.ti.com
SLUS336A –JUNE 1998–REVISED DECEMBER 2016
Product Folder Links: UC1854 UC2854 UC3854
Submit Documentation FeedbackCopyright © 1998–2016, Texas Instruments Incorporated
5 Device Comparison Table
PARAMETER UC3854 UC3854A UC3854B
Supply current, OFF 2-mA maximum 400-µA maximum 400-µA maximum
Supply voltage (V
CC
) 35-V maximum 22-V maximum 22-V maximum
VCC turn-on threshold 16-V typical 16-V typical 10.5-V typical
VCC UVLO hysteresis 6-V typical 6-V typical 0.5-V typical
Current amplifier bandwidth 1-MHz typical 5-MHz typical 5-MHz typical
Current amplifier offset 4-mV, –4-mV maximum 0-mV, –4-mV maximum 0-mV, –4-mV maximum
MULTOUT voltage (high) 2.5-V typical 5-V typical 5-V typical
Multiplier gain tolerance Not specified –0.9 to –1.1 –0.9 to –1.1
ENABLE propagation delay Not specified 300-ns typical 300-ns typical
VSENSE input 7.5 V 3 V 3 V
IAC voltage 6-V typical 0.5-V typical 0.5-V typical
Voltage amplifier clamp — Internal Internal
Current amplifier clamp — Internal Internal
VREF good circuitry — Internal Internal
6 Pin Configuration and Functions
DW, J, and N Packages
16-Pin SOIC, CDIP, and PDIP
Top View
FN Package
20-Pin PLCC
Top View
SET T
1.25
F
R C
=
´
4
UC1854
,
UC2854
,
UC3854
SLUS336A –JUNE 1998–REVISED DECEMBER 2016
www.ti.com
Product Folder Links: UC1854 UC2854 UC3854
Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated
Pin Functions
PIN
I/O DESCRIPTION
NAME
CDIP,
PDIP,
SOIC
PLCC
CAOUT 3 4 O
Current amplifier output. This is the output of a wide-bandwidth operational amplifier that senses line
current and commands the pulse-width modulator (PWM) to force the correct current. This output
swings close to GND, allowing the PWM to force zero duty cycle when necessary. The current
amplifier remains active even if the IC is disabled. The current-amplifier output stage is an NPN
emitter-follower pullup and an 8-kΩ resistor to ground.
CT 14 18 I
Oscillator timing capacitor. A capacitor from CT to GND sets the PWM oscillator frequency.
Use Equation 1:
(1)
ENA 10 13 I
Enable. ENA is a logic input that enables the PWM output, voltage reference, and oscillator. ENA
also releases the soft-start clamp, allowing SS to rise. When not in use, connect ENA to a 5-V supply
or pull ENA high with a 22-kΩ resistor. The ENA pin is not intended to be used as a high speed
shutdown to the PWM output.
GND 1 2 —
Ground. All voltages are measured with respect to GND. VCC and VREF must be bypassed directly
to GND with an 0.1-µF or larger ceramic capacitor. The timing capacitor discharge current also
returns to this pin, so the lead from the oscillator timing capacitor to GND must also be as short and
as direct as possible.
GTDRV 16 20 O
Gate drive. The output of the PWM is a totem-pole MOSFET gate driver on GTDRV. This output is
internally clamped to 15 V so that the IC operates with V
CC
as high as 35 V. Use a series gate
resistor of at least 5 Ω to prevent interaction between the gate impedance and the GTDRV output
driver that might cause the GTDRV output to overshoot excessively. Some overshoot of the GTDRV
output is always expected when driving a capacitive load.
IAC 6 8 I
Input AC current. This input to the analog multiplier is a current. The multiplier is tailored for very low
distortion from this current input (IAC) to MULTOUT, this is the only multiplier input that must be used
for sensing instantaneous line voltage. The nominal voltage on IAC is 6 V, in addition to a resistor
from IAC to rectified 60 Hz, connect a resistor from IAC to REF. If the resistor to VREF is one-fourth
of the value of the resistor to the rectifier, then the 6-V offset is cancelled, and the line current has
minimal cross-over distortion.
ISENSE 4 5 I
Current-sense minus. This is the inverting input to the current amplifier. This input and the non-
inverting input, MULTOUT, remain functional down to and below GND. Take care to avoid taking
these inputs below –0.5 V because they are protected with diodes to GND.
MULTOUT 5 7 I/O
Multiplier output and current-sense plus. The output of the analog multiplier and the non-inverting
input of the current amplifier are connected together at MULTOUT. The cautions about taking
ISENSE below –0.5 V also apply to MULTOUT. As the multiplier output is a current, this is a high-
impedance input similar to ISENSE, so the current amplifier can be configured as a differential
amplifier to reject GND noise. Figure 9 shows an example of using the current amplifier differentially.
NC —
1, 6,
11, 16
— No connection
PKLMT 2 3 I
Peak current limit. The threshold for PKLMT is 0 V. Connect this input to the negative voltage on the
current-sense resistor as shown in Figure 9. Use a resistor to VREF to offset the negative current-
sense signal up to GND.
RSET 12 15 I
Oscillator charging current and multiplier limit set. A resistor from RSET to GND programs oscillator
charging current and maximum multiplier output. Multiplier output current does not exceed 3.75 V
divided by the resistor from RSET to GND.
SS 13 17 I
Soft start. SS remains at GND as long as the device is disabled or V
CC
is too low. SS pulls up to
over 8 V by an internal 14-mA current source when both V
CC
becomes valid and the IC is enabled.
SS acts as the reference input to the voltage amplifier if SS is below VREF. With a large capacitor
from SS to GND, the reference to the voltage regulating amplifier rises slowly, and increases the
PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS quickly
discharges to ground and disables the PWM.
VAOUT 7 9 O
Voltage amplifier output. This is the output of the operational amplifier that regulates output voltage.
Like the current amplifier, the voltage amplifier remains active even if the IC is disabled with either
ENA or VCC. This means that large feedback capacitors across the amplifier stay charged through
momentary disable cycles. Voltage amplifier output levels below 1 V inhibit multiplier output. The
voltage amplifier output is internally limited to approximately 5.8 V to prevent overshoot. The voltage
amplifier output stage is an NPN emitter-follower pullup and an 8-kΩ resistor to ground.
5
UC1854
,
UC2854
,
UC3854
www.ti.com
SLUS336A –JUNE 1998–REVISED DECEMBER 2016
Product Folder Links: UC1854 UC2854 UC3854
Submit Documentation FeedbackCopyright © 1998–2016, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME
CDIP,
PDIP,
SOIC
PLCC
VCC 15 19 —
Positive supply voltage. Connect VCC to a stable source of at least 20 mA above 17 V for normal
operation. Also bypass VCC directly to GND to absorb supply current spikes required to charge
external MOSFET gate capacitances. To prevent inadequate GTDRV signals, these devices are
inhibited unless V
CC
exceeds the upper undervoltage-lockout threshold and remains above the lower
threshold.
VREF 9 12 O
Voltage reference output. VREF is the output of an accurate 7.5-V voltage reference. This output is
capable of delivering 10 mA to peripheral circuitry and is internally short-circuit current limited. VREF
is disabled and remains at 0 V when V
CC
is low or when ENA is low. Bypass VREF to GND with an
0.1-µF or larger ceramic capacitor for best stability.
VRMS 8 10 I
RMS line voltage. The output of a boost PWM is proportional to the input voltage, so when the line
voltage into a low-bandwidth boost PWM-voltage regulator changes, the output changes immediately
and slowly recovers to the regulated level. For these devices, the VRMS input compensates for line
voltage changes if it is connected to a voltage proportional to the RMS input line voltage. For best
control, the VRMS voltage must stay between 1.5 V and 3.5 V.
VSENSE 11 14 I
Voltage amplifier inverting input. This is normally connected to a feedback network and to the boost
converter output through a divider network.
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages with respect to GND.
(3) All currents are positive into the specified terminal.
(4) ENA input is internally clamped to approximately 14 V.
(5) Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)(3)(4)(5)
MIN MAX UNIT
Supply voltage VCC 35 V
Input Voltage
VSENSE, VRMS 11
VISENSE, MULTOUT 11
PKLMT 5
Gate driver current Input current
50% duty cycle 1.5
A
Continuous 0.5
Input current RSET, IAC, PKLMT, ENA 10 mA
Power dissipation 1 W
Storage temperature, T
stg
–65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2500
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
±1500
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