安森美半导体ESD保护器件PACVGA105-D 数据手册pdf,安森美半导体ESD保护器件PACVGA105-D 数据手册
PINDESCRIPTIONS LEAD(s) NAME DESCRIPTION HSYNC_OUT Horizontal sync signal buffer output Connects to the video connector side of the horizontal sync line HSYNC Horizontal sync signal buffer input. Connects to the VGA Controller side of the horizontal sync line 3,11 GNDD Digital ground reference supply pin RGB Vpgr supply pin. This is an isolated supply pin for the R, G and B ESd protection circuits Blue signal video protection channel. This pin is typically tied to the b video line between the VGA controller device and the video connector 6 Green signal video protection channel This pin is typically tied to the g video line between the VGA controller device and the video connector 7 R Red signal video protection channel. This pin is typically tied to the R video line between the VGA controller device and the video connector 8 GNDA Analog ground reference supply pin 9,16 Vcc supply pin. This is the main supply input for the DDC_CLK and DDC_DATA pullup resistors and ESD protection circuits. It is also connected to the sync buffers and to the ESD rotection diodes present on the hsYNc out and VSYNc OUT lines 10 DDC_DATA DDC data pin 12 DDC_CLK DDC clock pin 13 Vaux supply pin this is the supply input for the 50kQ2 pullups connected to the hSync and VSYNC buffer inputs 14 VSYNC Vertical sync signal buffer input connects to the vga controller side of the vertical sync line 15 VSYNC_OUT Vertical sync signal buffer output Connects to the video connector side of the vertical sync line Ordering Information PART NUMBERING INFORMATION Standard finish Lead-free Finish Pins Package Ordering Part Part Marking Ordering Part Numbe Number Part Marking 16 QSOP PACVGA105Q PACVGA105Q PACVGA105QR PACVGA105QR Note 1: Parts are shipped in Tape Reel form unless otherwise specified Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS Vcc, VBGB,VAux Supply Voltage Inputs GND-05]to+6.0 Diode Forward Current(one diode conducting at a time 0 mA DC Voltage at Inputs R G.B [GND-0.5]tce+0.5 V HSYNC VSYNC IGND-0.5]to[vaux +0.5 DDC CLK DDC DATA [GND-05]to N +0.5] V Operating Temperature Range 0to+70 °C Storage Temperature range 40to+150 C Package Power Rating 750 STANDARD OPERATING CONDITIONS SYMBOL PARAMETER MIN MAX UNITS Main Supply Voltage 4.5 5.5 RGD RGB Supply voltage 1.7 3.7 VAUX Auxiliary Supply Voltage 2.9 3.7 V vH Logic High Input Voltage( Note 1) 2.0 V Logic Low Input Voltage Note 1) 0.8 V Input Voltage RGB 0 HSYNC, VSYNC 0 DDC CLK DDC DATA 0 V High Level Output Current(Note 1) -8 Low Level Output Current(Note 1) 8 A T Free-air Operating temperature 0 十 C Note 1: These parameters apply only to the HSYNc and VSYNC signals ELECTRICAL OPERATING CHARACTERISTICS SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Diode Forward voltage =10mA 1.0 Logic High Output Voltage =-4mA,v=45V 4.0 Logic Low Output Voltage =4mA.V=4.5V 0.4 iNPut Current R, G and b pins V=3.63V,V=V or gND LA HSYNC, VSYNC pins HSYNC, VSYNC pi L1x=363V,y LA AUx =3.63V, VIN=GND -30 -72595 LA lcc Vcc Supply Current Vcr=5.5V; Vaux=Ver=2.97V; All inputs 100 LA and outputs floating Von Supply current R, G and B pins at V or GND; All 10 A inputs and outputs floating Input Capacitance Note 2 applies for all cases R, G and B pins 5 HSYNC, VSYNC pins 10 DDC_DATA, DDC_CLK pins 5 R Pull-up Resistance DDC DATA, DDC CLK pins 8 1.98 ko I ESD Withstand Voltage =5V;V8=3.3V; 8 KV V=3.3V: note 3 SYNC Buffer L=>H C=50pF;V=5.0V; 70150ns Propagation Delay R=500Q2: Note SYNC Buffer H=> L C=50pF;V=5.0V; 7.0 15.0 n PHL Propagation Delay R=500Q2; Note 4 tt SYNC Buffer Output Rise Fall CL=50pF: Vc=5.0V; 7.0 ns Times R= 5000: Note 4 Note 1: All parameters specified over standard operating conditions unless otherwise noted Note 2: Measured at 1MHz. R/G/B inputs biased at 1.65V with VeGr=3.3V DDC_CLK and DDC_Data biased at 2. 5V with V=5V HSYNC and VSYNC inputs biased at vaux or GND with Vaux=3.3v and Vu= 5v Note 3: Per the lEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VaaB and Vcc must be bypassed to GNd via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin ESD pulse is applied between the applicable pins and GND. esd pulse can be positive or negative with respect to GND. Applicable pins are: R, G, B, HSYNC OUT, VSYNC_ OUT, DDC CLK and DDC DAtA. the HSYNC and VSYNc inputs are ESD protected to the industry standard 2kv per the Human Body Model ( MIL-STD-883, Method 3015 Note 4: Applicable to the SYNc buffers only. Input signals swing between ov and 3.0V, with rise and fall times s 5ns Guaranteed by correlation to buffer output drive currents Application Information o videρ DAC VI 53.3 Ouf 602uF 13 H-Sync HSYNC GNDA V-Sync 14 VSYNC GNDD 3,11 s DDc Data DDC DATA DDC Clk DDC CLK oo DIGITAL ANALOG GND Red PACVGA105 Blu HSYNC OUT VSYNC OUT H15 R 6G OH-Sync VF-VIDEO EMI Filter SF“ SYNC EN| Filter B v-sync o DDC Data O DDC Clk a Green Blue Figure 1. Typical Connection Diagram GNDA, the negative voltage rail for the R, G and b diodes is not connected internally to GNDD. GNDA should ideally be connected to the ground of the video dac IC. This will prevent any ground bounce caused by digital signals from injecting noise onto the R, G and B signals. Analog gnd and digital gnd are typically connected on the printed circuit board Mechanical details QSoP Mechanical Specifications PACVGA105 devices are packaged in 16-pin QSoP packages. Dimensions are presented below For complete information on the QsoP-16 package, see the California Micro Devices QSoP Package Information document PACKAGE DIMENSIONS TOP VIEW D Package QSOP (JEDEC name is SSOP) 1514131211109 Pins 16 日目目日日日日 Millimeters Inches Dimensions E Pin 1 Marking Min Max Mir Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 00040.010 12345678 0.20 0.30 0.008 0.012 BcD 0.18 0.25 0.007 0.010 SIDE VIEW 4.80 5.00 0.189 0.197 3.81 3.98 0.150 0.157 SEAT ING Al PLANE 0.64 BSC 0.025BSc H 5.79 6.19 0228 0.244 END VIEW 0.40 1.27 00160.050 per tube 100 pcs per tape 2500 pcs and reel Controlling dimension: inches Package Dimensions for QSoP-16 This is an approximate number which may vary ON Semiconductor and oNare registered trademarks of Semiconductor Components Industries, LLC (SCILLC) SCILLC reserves the right to make changes without further notice to any oroducts herein. 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