安森美半导体ESD保护器件CM1234-D 数据手册.pdf

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安森美半导体ESD保护器件CM1234-D 数据手册pdf,安森美半导体ESD保护器件CM1234-D 数据手册
CM1234 In the CM1234 Pico Guard XS architecture, the signal line leading the connector to the ASIC routes through the CM1234 chip which provides 100Q matched differential channel characteristic impedance that helps optimize 10002 load impedance applications such as the HDMI high speed data lines Note: When each of the channels are used individually for single-ended signal lines protection, the individual channel provides 50@2 characteristic impedance matching The load impedance matching feature of the cM1234 helps to simplify system designer' s pcb layout considerations in impedance matching and also eliminates associated passive components The route through the Pico Guard Xs architecture enables the CM1234 to provide matched impedance for the signal path between the connector and the ASIC. Besides this function, this circuit arrangement also changes the way the parasitic inductance interacts with the esd protection circuit and helps reduce the lbesiDua current to the ASIC ESD Stike 三SD Protecton ASIC DevIce Connector SAN RESDUAL igure 1. Standard ESD Protection Device Block Diagram Rev.3Page3of13www.onsemi.com CM1234 The Pico Guard Xs Architecture Advantages Figure 2 illustrates a standard Esd protection device. The inductor element represents the parasitic inductance arising from the bond wire and the pCb trace leading to the ESd protection diodes Conrector ASIC Bond vre Ir duchang 三5D Figure 2. Standard ESD Protection Model Figure 3 illustrates a standard ESD protection device. The inductor element represents the parasitic inductance arising from the bond wire and the pcb trace leading to the ESd protection diodes Connector ESD Deyoe Figure 3. CM1234 Pico Guard Xs ESD Protection Model Rev.3Page4of13www.onsemi.com CM1234 CM1234 Inductor Elements In the CM1234 PicoGuard XS architecture, the inductor elements and ESD protection diodes interact differently compared to the standard esd model In the standard ESD protection device model, the inductive element presents high impedance against high slew rate strike voltage, i. e. during an ESD strike. The impedance increases the resistance of the conduction path leading to the ESd protection element. this limits the speed that the esd pulse can discharge through the Esd protection element In the Pico Guard Xs architecture, the inductive elements are in series to the conduction path leading to the protected device. The elements actually help to limit the current and voltage striking the protected device First the reactance of the inductive element L1. on the connector side when an esd strike occurs. acts in the opposite direction of the ESD striking current. This helps limit the peak striking voltage. Then the reactance of the inductive element, L2, on the aSic side forces this limited ESd strike current to be shunted through the ESD protection diodes. At the same time, the voltage drop across both series element acts to lower the clamping voltage at the protected device terminal Through this arrangement, the inductive elements also tune the impedance of the esd protection element by cancelling the capacitive load presented by the esd diodes to the signal line. This improves the signal integrity and makes the overall ESD protection device more transparent to the high bandwidth data signals passing through the channel The innovative Pico Guard Xs architecture turns the disadvantages of the parasitic inductive elements into useful components that help to limit the eSd current strike to the protected device and also improves the signal integrity of the system by balancing the capacitive loading effects of the Esd diodes. At the same time, this architecture provides an impedance matched signal path for 50Q2 loading applications Board designs can take advantage of precision internal component matching for improved signal integrity, which is not otherwise possible with discrete components at the system level. This helps to simplify the PCB layout considerations by the system designer and eliminates the associated passive components for load matching that is normally required with standard ESd protection circuits Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to either the Zener diode or to ground. This embedded Zener diode also serves to eliminate the need for a separate bypass capacitor to absorb positive ESD strikes to ground. The Cm1234 protects against ESD pulses up to +1 8kv contact per the IEC 61000-4-2 standard Rev.3Page5of13www.onsemi.com CM1234 PACKAGE/PINOUT DIAGRAMS Bottom View(solder Side) or 1 Cut 1 n2+ cut 2. or 3+ 13+ or 3. 3 的4+ In 4- Note: 1)This drawing is PIN DESCRIPTIONS Pin ame Description In 1+ Bidrectional clamp to asic (inside system In 1 Bidrectional Clamp to ASIC (inside system In 2 Bidrectional Clamp to asic (inside system) 4 In 2 Bidrectional Clamp to AsiC (inside system 5 In 3+ Bidrectional Clamp to ASIC (inside systel 6 Bidrectional Clamp to asic (inside system In 4t Bidrectional Clamp to AsIC (inside system In 4 Bidrectional Clamp to asic (inside system 9 Out 4 Bidrectional Clamp to Connector(outside system) 10 Out 4+ Bidrectional Clamp to Connector(outside system) out 3 Bidrectional clamp to Connector (outside system) 12 out 3+ Bidrectional clamp to connector(outside system 13 Out 2 Bidrectional Clamp to Connectoroutside system) 14 Out 2+ Bidrectional Clamp to Connector (outside system) 15 Out 1 Bidrectional Clamp to Connector (outside system 16 Out 1+ Bidrectional Clamp to connector(outside system PAD GND Ground return to shield Ordering Information PART NUMBERING INFORMATION PIN PACKAGE ORDERING PART NUMBER (LEAD-FREE FINISH PART MARKING 16 TDFN-16 CM123408DE CM123408 Note 1: Parts are shipped in tape& reel form unless otherwise specified Rev.3Page6of13www.onsemi.com CM1234 Specifications ABSOLUTE MAXIMUM RATINGST PARAMETER RATING UNITS Operating Temperature Range -40to+85 Storage Temperature Range 65to+150 Breakdown Voltage 6 (Positive) Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS yo Voltage relative to gnD 0.5 5 IN Continuous Current through signal pins 100 mA (IN to OUt)1000 Hr Channel Leakage current T=25C; V,=oV,ReCt= 5V 0.1 1.0 ESD Protection-Peak discharge voltage at any channel input, in system a) Contact discharge per IEC 61000-4-2 Standard T=25℃ 15 and b)Air discharge per IEC 61000-4-2 Stan- T,=25C ±20 KV dard Residual ESD Peak Current on RDUP EcC61000-428kV Resistance of Device Under Protection) RDUP=52 T=25C 2.5 A Channel Clamp Voltage p=1A,T=25℃, Channel clamp voltage per IEC 61000-4-t,=8/20uS 5 Standard) Positive Transients Negative Transients Dynamic Resistance 1A,TA=25C; Positive Transients t=8/20S 0.44 Negative Transients 0.38 2 Differential Channels pair characteristic T:=200ps 100 impedance Rev.3Page7of13www.onsemi.com CM1234 SYMBOLPARAMETER CONDITIONS MIN TYP MAX UNITS AZo Channel-to-Channel Impedance Match T:=200ps % (Differential) ZHANNEL Individual Channel Characteristic Imped- T:=200ps 50 ance in Single-ended Connection AZGMANEL Channel-to-Channel Impedance MatchTa=200ps 2 % (Individual) Note 1: All parameters specified at Ta=-40C to +85C unless otherwise noted Performance Information Graphical Comparison and Test Setup Figure 4 shows that the CM1234( PicoGuard XS ESD protector) lowers the peak voltage and clamping voltage by 45% across a wide range of loading conditions in comparison to a standard Esd protection device. Figure 5 also indicates that the DUP/ASic protected by the CM1235 dissipates less energy than a standard ESd protection device. This data was derived using the test setups shown in Figure 6 带·带物 0.S cM123-08 DEwe 0.2 10 RDUP (Q) Figure 4. Normalized vPeak(8KVIEC-61000 4-2 ESD Contact Strike) VS Loading(RDUP) Rev.3Page8of13www.onsemi.com CM1234 1.2 08 0.6 cM123403 · TD ESD DeDe 04 0.2 2 16 18 20 RDUP(Q) Figure 5. Normalized Residual current into dUP VS RDUP* RDUP is the emulated Dynamic Resistance(load )of the device Under Protection(DUP) volts: vcll32e F。2 TECE10C-4-2 P。2 Test sandard: cM1234 Devee Under vceUrcer Freest cr(oUP S器rd:7 Eocene Curer: Standard ESD CM1234 Test Setup Device Test Setup Figure 6. Test Setups: Standard Device (Left)and CM1234 (Right) Rev.3Page9of13www.onsemi.com CM1234 CM1234 Application and guidelines As a general rule, the CM1234 ESD protection array should be located as close as possible to the point of entry of expected electrostatic discharges with minimum PCb trace lengths to the ground planes and between the sig- nal input and the esd device to minimize stray series inductance cM1234 creutry Under Ps:8=83 Fr。::n curempue=r Lre Ben? Crenel channe Cutout Goun Ral Figure 8. Application of Positive ESD Pulse Between Input Channel and Ground o oˉ0 .. HD Figure 9. Typical PCB Layout Additional Information See also California Micro Devices Application Note AP209, "Design Considerations for ESD Protection, " in the Applicationssectionatwww.calmicro.com Rev.3Page10of13www.onsemi.com

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