安森美半导体ESD保护器件CM1224-D 数据手册.pdf

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安森美半导体ESD保护器件CM1224-D 数据手册pdf,安森美半导体ESD保护器件CM1224-D 数据手册
CM1224 Ordering Information PART NUMBERING INFORMATION Lead-free Finish t of channels Leads Package Ordering Part Number Part Marking SOT143-4 CM122402SR L242 6 SOT23-6 CM1224-0450 L244 10 MSOP-10 CM122404MR L243 Note 1: Parts are shipped in Tape Reel form unless otherwise specified Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS Operating Supply Voltage(V, -V) 60 Operating Temperature Range 40to+85 Storage Temperature range 65to+150 ℃ Dc Voltage at any channel input V-0.5)to(v。+0.5 STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS Operating Temperature Range -40to+85 Package Power Rating SOT23-3, SOT143-4, SOT23-5 and SoT23-6 Packages 225 MSOP-10 Package 400 mW Rev.3Page3of14www.onsemi.com CM1224 ELECTRICAL OPERATING CHARACTERISTICS SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage(Vp.-VM) 3.3 5.5 lp Operating Supply Current (V。V)=33V 8.0 μ A V Diode Forward Voltage l=8mA;T=25 Top Diode 0.600.800.95 Bottom diode 0600.800.95 LEAK Channel Leakage Current T=25°:V=5V.V=0V ±0.1±1.01A Channel Input Capacitance At1MHz,V-33V,V-0V,0.600.700.80 F V=1.65V △C Channel Input Capacitance Matching At 1 MHZ, V=3.3V, v=oV, 0.02 F N V.=1.65V ESD Protection- Peak Discharge voltage at any channel input, in system Contact discharge per IEC 61000-4-2 standard Notes2and3;T=25℃ kV Channel Clamp Voltage T=25%,l。=1A Positive Transients tp=8/20μS;Note3 +10.0 V Negative Transients R Dynamic resistance Ipp=1A, t,=8/20uS Positive Transients Any l/O pin to Ground 1.08 Negative Transients Note 3 0.66 Note 1: All parameters specified at TA=-40C to +85C unless otherwise noted Note 2: Standard IEC 61000-4-2 with Goischane=150pF, Roischaroa 33022, V,=3.3v,V grounded Note 3: These measurements pertormed with no external capacitor on V, ( p floating Rev.3Page4of14www.onsemi.com CM1224 Performance Information Input Channel Capacitance Performance Curves 0 1.5 0.5 00 a.0 05 10 1.5 25 3.0 3.5 In put voltage(vI ypical Variation of CIN VS. VIN (f=1MHz, vp=3.3v, n=0v 10k between Vp and 3. 3w supply, 0. 1 uF chip capacitor between Wp and WN. 25 C) 0,95 090 0yDG Inout blaa 0.80 e=1.s5/ DC Input Blas 0.T5 0,70 06 50 75 100 Temperature(CI Typical Variation of CIN vS. Temp =1 MHz, VIN30mv,Vp=3.3n, VN=0v, 10k2 batween 'p and 3. 3v supply, 0. 1 uF chip capacitor between vp and VHl Rev.3Page5of14www.onsemi.com CM1224 Performance Information(cont d) Typical Filter Performance(nominal conditions unless specified otherwise, 50 Ohm Environment 日2:是109MAG 1dB!REF0d自 1一.口了d日 F00ooob种z 1 de 2d日 3de d de de -6dB 7de -B de 9de 1 dB 3 100 10002000 60 FREQUENCY(MHzl Figure 1. Insertion Loss (S21)VS Frequency (oV DC Bias, Vp=3.3v) 0dB21 1。gMAG 1d日,PEF日 斗-.Da4日日 000|ap -1 dB O 5de T dB -B da dB 100 10002000000 FREQUENCY(MHzl Figure 2. Insertion Loss(S21)VsFrequency(2.5V DC Bias, V=3.3v) Rev.3paGe6of14www.onsemi.com CM1224 Application Information Design Considerations To realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input(typically a connector) and the ESD protection device. Application of Positive ESD Pulse between Input Channel and ground illustrates an example of a positive ESd pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L, and L,. The voltage V on the line being protected is Fwd voltage dt D d(een) dt +L, x d(ea)/dt where IEsp is the ESD current pulse, and VSupply is the positive supply voltage An ESd current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from 0 to 30 Amps in 1ns. Here d(esp)/dt can be approximated by Ales/At, or 30/ (1x10). So just 10nH of series inductance( L, and L, combined will lead to a 300V increment in v, Similarly for negative ESD pulses, parasitic series inductance from the V pin to the ground rail will lead to drastically increased negative voltage on the line being protected The CM1224 has an integrated Zener diode between v and V. this greatly reduces the effect of supply rai inductance L, on V by clamping v, at the breakdown voltage of the Zener diode. However, for the lowest possible VcL, especially when V is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22uF ceramic chip capacitor be connected between v, and the ground plane As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned earlier should be as close to the v pin of the protection array as possible, with minimum pcb trace lengths to the power supply ground planes and between the signal input and the esd device to minimize stray series inductance Additional Information See also California Micro Devices Application Note AP209, " Design Considerations for ESD Protection, "in the Applicationssectionatwww.calmicro.com Ps瑟 PFLY FLL PATHOF EBDCUFRENT PULSE erp LEE BEIN 022F FROTELTEB SYSTEM OR CIFCLTEY BENO CHEL§ PROTETED IPL 12133 ER JEDFAL HSSSEL平 Figure 3. Application of Positive ESD Pulse between Input Channel and Ground Rev.3Page7of14www.onsemi.com CM1224 Mechanical Details The CM1224 is available in SOT143-4, SOT23-6, and MsoP-10 packages with a lad-free finishing option. The various package drawings are presented below SOT143-4 Mechanical Specifications Dimensions for CM1224-02SR devices supplied in 4-pin SoT143 packages are presented below PACKAGE DIMENSIONS Mechanical Package Diagrams TOP VIEW Package SOT143 Pins 4 Dimensions Millimeters Inches E1 E Min Max Min Max 0.80 1.22 0.031 0.048 A1 0.05 0.15 0.002 0.006 b 0.30 0.50 0.012 0.019 SIDE VIEW b2 0.89 0.030 0.035 0.08 0.20 0.003 0.008 A D 2.80 3.04 0.110 0.119 b2 2.10 2.64 00820.103 A1 E1 1.20 1.40 0.047 0.055 END VIEW 1.92 BSC 0.075BSC e1 0.20 BSC 0.008BSC 0.4 0.6 0.016 0.024 L L1 0.54 REF 0.021REF per tape and reel 3000 pieces Package Dimensions for SoT143 Controlling dimension: millimeters Rev.3Page8of14www.onsemi.com CM1224 Tape and Reel Specifications PACKAGE SIZE POCKET SIZE(mm) TAPE WIDTHREEL QTY PER PART NUMBER(mm) B.XAXK W DIAMETER REEL CM122402SR292X2.37×1.01260X315X1208m 178mm(7")300 4mm 4mm 10 Pitches cum」aive P。 5 ance on a lT c ave 不 T or tape feeder reference gnly incl a cre Embossment P1 Center lines Concentric atound e User direction of feed Rev.3Page9of14www.onsemi.com CM1224 Mechanical Details(contd) SOT23-6 Mechanical Specifications CM1224-04s0 devices are packaged in 6-pin SoT23 packages. Dimensions are presented below Mechanical Package Diagrams PACKAGE DIMENSIONS TOP VIEW Package SoT23-6 JEDEC name is Mo-178) e1 Pins 6 Millimeters Inches Dimensions E1 E Min Max Min Max A 1.45 0.0571 0.00 0.15 0.00000.0059 0.30 0.50 0.01180.0197 SIDE VIEW 0.08 0.22 0.00310.0087 D 2.75 3.05 0.10830.1201 A E 2.60 3.00 0.10240.1181 E1 1.45 1750.05710.0689 0.95 BSC 0.0374BSC END VIEW e1 1.90 BSC 0.0748BSc 0.30 0.600011800236 L1 0.60 REF 0.0236REF #f per tape 3000 pieces and reel Controlling dimension: millimeters Package Dimensions for SoT23-6 Rev.3Page10of14www.onsemi.com

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