安森美半导体ESD保护器件CM2030-D 数据手册.pdf

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安森美半导体ESD保护器件CM2030-D 数据手册pdf,安森美半导体ESD保护器件CM2030-D 数据手册
CM2030 PIN DESCRIPTIONS ESD Level DESCRIPTION 4.35 TMDS D2+ 8KV MDS 0. 9pF ESD protection 6.33 TMDS D2 kva TMDS 0. 9pF ESD protection 7,32 TMDS D1+ TMDS 0. 9pF ESD protection. 9,30 TMDS D1 TMDS 0.9pF ESD protection 10.29 TMDS DO+ 8k↓ TMDS 0.9pF ESD protection 12.27 TMDS DO- 8kV TMDS 0.9pF ESD protection 13.26 TMDS CK+ ITMDS 0 9pF ESD protection 15,24 TMDS CK 8kV MDS 0. 9pF ESD protection CE REMOTE IN CE SUPPLY referenced logic level in 23 CE REMOTE oUT 8kV 5V SUPPLY referenced logic level out plus 1OpF ESD DDC CLK IN V SUPPLY referenced logic level in 22 DDC CLK OUT 5V_SUPPLY referenced logic level out plus 10pF ESD. DDC DAT IN V SUPPLY referenced logic level in 21 DDC DAT OUT 8kV 5V_SUPPLY referenced logic level out plus 10pF ESD.6 19 HOTPLUG DET iN 2kV V SUPPLY referenced logic level i 20 HOTPLUG DET OUT 8kV V_SUPPLY referenced logic level out plus 10pF ESD. A O. F bypass ceramic capacitor is recommended on this pll 2 LV SUPPLY Bias for CE/DDC/ HOTPLUG level shifters 37 CE SUPPLY 2k2 CEC bias voltage. Previously CM2020 ESD_BYP pin 5V SUPPLY 2kV Current source for 5V_ oUT, VREF for DDC IC voltage references and bias for 8kV ESD pins 38 5V OUT 8kV 55mA minimum overcurrent protected 5V output. This output must be bypassed with a 0.1 uF ceramic capacitor. 5,8, 11, GND/TMDS GND N/A GND reference 14,25 28,31,34,36 Note 1: These 2 pins need to be connected together in- line on the PCB. See recommended layout diagram Note 2: This output can be connected to an external 0. 1 uF ceramic capacitor/pads to maintain backward compatibility with the CM2020 Note 3: Standard IEC 61000-4-2, CoIecuAnc-=150pF, RoscuAncr=330Q2, 5V SUPPLY and LV SUPPLY within recommended operating conditions, GND=OV, 5V_oUT (pin 38), and HOTPLUG DET_ OUT (pin 20) each bypassed with a 0.1uF ceramic capacitor connected to GND Note 4: Human Body Model per MIL-STD-883, Method 3015, Corcuancr=100pF, Roscuancr =1.5k Q2, 5v sUPPLYand LV SUPPLY within recommended operating conditions, GND=OV, 5V_OUT(pin 38), and HOTPLUG_ DET_OUt(pin 20) each bypassed with a 0. 1pF ceramic capacitor connected to GND Note 5: These pins should be routed directly to the associated gnd pins on the hdmi connector with single point ground vias at the connector Note 6: The slew-rate control and active acceleration circuitry dynamically offsets the system capacitive load on these pins Rev.5Page3of17www.onsemi.com cM2030 Backdrive Protection and isolation Backdrive current is defined as the undesirable current flow through an l/o pin when that io pins voltage exceeds the related local supply voltage for that circuitry. This is a potentially common occurrence in multimedia entertainment systems with multiple components and several power plane domains in each system For example, if a dvd player is switched off and an HdMi connected tv is powered on, there is a possibility of reverse current flow back into the main power supply rail of the dvd player from pull-ups in the TV. As little as a few milliamps of backdrive current flowing back into the power rail can charge the dVD player's bulk bypass capacitance on the power rail to some intermediate level. If this level rises above the power-on-reset (POR) voltage level of some of the integrated circuits in the dVd player, then these devices may not reset properly when the DVD player is turned back on If any soc devices are incorporated in the design which have built-in level shifter and/or ESD protection structures, there can be a risk of permanent damage due to backdrive. In this case, backdrive current can forward bias the on-chip ESD protection structure. If the current flow is high enough, even as little as a few milliamps, it could destroy one of the soc chips internal dRC diodes, as they are not designed for passing DC To avoid either of these situations, the CM2030 was designed to block backdrive current, guaranteeing less than 5ua into any 0 pin when the l o pin voltage exceeds its related operating Cm2030 supply voltage LYSIPR↑ LY PFLT LOTVOLTAGE LOW YOLTAGE HDHIASK A息 HDMIASIC HIMIERDCE HDNISOLFCE HoNIES Figure 1. Backdrive Protection Diagram. Display data Channel(DDc)lines The DDC interface is based on the IC serial bus protocol for EDID configuration DYNAMIC PULLUPS Based on the HDMI specification, the maximum capacitance of the ddc line can approach 800pF(50pF from source, 50pF from sink, and 700pF from cable). At the upper range of capacitance values(i.e. long cables),it becomes impossible for the ddc lines to meet the I c timing specifications with the minimum pull-up resistor of 1.5kΩ. For this reason, the cm2030 was designed with an internal ic accelerator to meet the ac timing specification even with very long and non-compliant cables Rev.5Page4of17www.onsemi.com CM2030 The internal accelerator increases the positive slew rate of the DDC_CLK_ OUT and ddC_ DAT_ OUT lines whenever the sensed voltage level exceeds 0. 3*5V_SUPPLY(approximately 1.5V). This provides faster overall risetime in heavily loaded situations without overloading the multi-drop open drain ic outputs elsewhere DYNAMIC PULLUPS(CONTD) t口 HLLL L网 耐h 2,[p Figure 2. Dynamic DDC Pullups(Discrete- Top, CM2030-Bottom; 3. 3V ASIC -Left, 5V Cable-Right Figure 2 demonstrates the"worst case"operation of the dynamic CM2030 DDC level shifting circuitry(bottom) against a discrete NF ET common-gate level shifter circuit with a typical 1.5kw pullup at the source (top )Both are shown driving an off-spec, but unfortunately readily available 31 m HDMI cable which exceeds the 700pF HDMI specification. Some widely available HDMI cables have been measured at over 4nF When the standard i/od cell releases the nfet discrete shifter, the risetime is limited by the pullup and the parasitics of the cable, source and sink For long cables, this can extend the risetime and reduce the margin for reading a valid"high" level on the data line. In this case, an HDMI source may not be able to read uncorrupted data and will not be able to initiate a link With the CM2030's dynamic pullups, when the asic driver releases its ddc line and the"OUT line reaches at least 0. 3*VDD (of 5V_ SUPPLY), then the OUT active pullups are enabled and the cm2030 takes over driving the cable until the "OUT" voltage approaches the 5V sUPPLY rail The internal pass element and the dynamic pullups also work together to damp reflections on the longer cables and keep them from glitching the local ASIC IC LOW LEVEL SHIFTING 1C low-level shifting on the ddC CLK IN and DDC DAT IN lines for enhanced compatibil, es In addition to the Dynamic Pullups described in the previous section, the Cm2030 also incorporate proved Typical discrete NFET level shifters can advertise specifications for low anson but usually state relatively high VIs test parameters, requiring a switch' signal (gate voltage)as high as 10V or more. At a sink current of 4mA for the asIc on DDCXXIN, the CM2030 guarantees no more than 1 40mV increase to DDC_XX OUT, even with a switching control of 2.5v on LV SUPPLY Rev.5Page5of17www.onsemi.com cM2030 When 'C devices are driving the external cable, an internal pulldown on DDC_XX_iN guarantees that the VOL seen by the asIC on DDC_XX_IN is equal to or lower than DDC_XX_OUT Multiport DDC Multiplexing By switching LV SUPPLY, the DDC/HPD blocks can be independently disabled by engaging their inherent backdrive"protection. This allows N: 1 multiplexing of the low-speed hdMi signals without any additional FEt switches Consumer Electronics Control (CEC) The Consumer Electronics Control (ceC) line is a high level command and control protocol, based on a single wire multidrop open drain communication bus running at approximately 1kHz (See Figure 3 While the HDMI link provides only a single point-to-point connection, up to ten(10)cec devices may reside on the bus, and they may be daisy chained out through other physical connectors including other HDMI ports or other dedicated CEC links. The high level protocol of cec can be implemented in a simple microcontroller or other interface with any l/OD(input/open-drain)GPIO CEC RX一 VOD GPIO igure 3. Typical uC l/OD Driver To limit possible EMI and ringing in this potentially complex connection topology, the rise-and fall-time of this line are limited by the specification. However, meeting the slew-rate limiting requirements with additional discrete circuitry in this bi-directional block is not trivial without an additional rX/TX control line to limit the output slew-rate without affecting the input sensing(See Figure 4) CEC RX TX Slew Rate Limited 3-State Buffe TX EN Figure 4. Three-Pin External Buffer Control Simple Cmos buffers cannot be used in this application since the load can vary so much(total pullup of 27ke2 to less than 2kQ2, and up to 7. 3n f total capacitance The cm2030 targets an output drive slew-rate of less than 100mV/ms regardless of static load for the CEC line. Additionally, the same internal circuitry will perform active termination, thus reducing ringing and overshoot in entertainment systems connected to legacy or poorly designed cEc nodes Rev.5Page6of17www.onsemi.com CM2030 The CM2030's bi-directional slew rate limiting is integrated into the CEC level-shifter functionality thus allowing the designer to directly interface a simple low voltage CMos GPlo directly to the cec bus and simultaneously guarantee meeting all cec output logic levels and hDMI slew-rate and isolation specifications See Figure 5) CEC CEC V/F P cM2030 Figure 5. Integrated CM2030 Solution The CM2030 also includes an internal backdrive protected static pullup 120uA current source from the CE SUPPLY rail in addition to the dynamic slew rate control circuitry Figure 6 shows a typical shaped CM2030 CEC output (bottom) against a ringing uncontrolled discrete solution (top) Figure 6. CM2030 CEC Output Rev.5Page7of17www.onsemi.com cM2030 Hotplug Detect Logic The CM2030 ensures that the local ASIC will properly detect an HDMI compliant Sink. The current sink main- tains a local logic "low when no system is connected A valid pullup on the HdMi connector pin will overdrive the internal pulldown and deliver a logic high" to the local asIC CM2030 5V SUPPLY LV SUPPL HP N HP OUT 19 HDMI CONN Figure 7. Hotplug Detect Circuit Rev.5Page8of17www.onsemi.com CM2030 Ordering Information PART NUMBERING INFORMATION 38 TSSOP-38 CM2030-AOTR CM2030-AOTR Note 1: Parts are shipped in Tape& reel form unless otherwise specified Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER VCC5, VCCLV 6.0 dc Voltage at any channel Input GND-0.5]to[VCC+0.5] V Storage Temperature Range 65to+150 STANDARD (RECOMMENDED)OPERATING CONDITIONS SYMBOL PARAMETER 5V_SUPPLY Operating Supply Voltage 5.5 V SUPPLY Bias Supply Voltage CE_ SUPPLY Bias Supply Voltage 3 3.3 3.6 VVV Operating Temperature Range 40 85 Rev.5Page9of17www.onsemi.com cM2030 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ICC5 perating Supply Current DV SUPPLY= 5.0V 300350 A CEC OUT=3.3V, LV SUPPLY 3.3V, CE SUPPLY=3.3V, DDC=5V Note ICCL Bias Supply Current V SUPPLY=3.3V: Note 6 60 150 CCCE Bias Supply Current CE SUPPLY=3.3V, CEC OUT=0V; 60150 A Notes 6 and 7 ICEC Current source on CEC pin E SUPPLY-33V 111120128 IA μ VDROP 5V_OUT Overcurrent Out put V_SUPPLY=5.0V, IOUT=55mA 100 mv Drop 5V_OUT Short Circuit Cur 5V_SUPPLY=5.0V, 5V_OUT=GND90135175 nA ent limit IOFF OFF state leakage current, LV_SUPPLY=OV 0.1 A level shifting NFET IBACKDRIVECEc Current through Ce CE-REMOTE_IN=CE_SUPPLY< 0.1 1.8 A REMOTE OUT when CE REMOTE OUT powered down BACKDRIVETMDS Current through TMDS pins All Supplies =OV; TMDS_[2: 01+/ 0.1 LA hen powered down MDS CK+/= 4V BACKDRIVE5V_OUT Current through 5V_OUT l Supplies=OV: 5V_OUT_PIN 0.1 A when powered down 5V I BACKDRIVEDDC Current through All Supplies=OV 0.1 5 A DDC DAT/CLK_ OUT when DDC DAT/CLK OUT=5V powered down DDC_DAT/CLK_IN=OV IBACKDRIVEHOTPLUG Current through All Supplies =oV 0.1 5 LA HOTPLUG DET OUT when HOTPLUG DET OUT=5V powered down HOTPLUG IN=oV CECSL CEC Slew Limit Measured from 10-90% or 90-10% 0.260.65V/ CECRT CEC Rise Time Measured from 10-90% 26.4 250 Assumes a signal swing from o 3V CECFT CEC Fall Time Measured from 90-10% 50 us Assumes a signal swing from o 3V VACC Turn On Threshold of 12C/ oltage is 0. 3 +10%X 5V_Supply:[1.351.51.65 DDC Accelerator Note 2 VON(DDC_OUT) oltage drop across DDC V SUPPLY=3.3V, 3mA Sink at 150225 level shifter DDCIN, DDCOUT VACC VOL(DDC_IN) Logic Level (ASIC side)when pDC_OUT=0.4V 030.4 12C/DDC Logic Low Applied; LV SUPPLY=3. 3V, 1.5kS pullup on ( 12C pass-through compatibility) DDC OUT to 5.0V: Note 2 tr (DDC) DDC OUT Line Risetime, DDC IN floating, us VACC <VDDC OUT< LV_ SUPPLY=3. 3V, 1. 5kS2 pullup on Rev.5Page10of17www.onsemi.com

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