安森美半导体ESD保护器件NUP2114UCMR6-D 数据手册pdf,安森美半导体ESD保护器件NUP2114UCMR6-D 数据手册
NUP2114UCMR6 lEC 61000-4-2 Spec IEC61000-4-2 Waveform Test First Peak Voltage Current Current at Current at 100% Level (kv) (A)60ns(A) 7.5 4 4 I@ 30 ns 3 225 12 8 30 16 l@60 10% 0.7 ns to 1 ns Figure 3. IEC61000-4-2 Spec ESD Gun TVS Oscilloscope 吕吕吕吕○ 50g □口口口■ Cable 50g ○O Figure 4. Diagram of ESD Test Setup The following is taken from Application Note systems such as cell phones or laptop computers it is not AND8308/D-Interpretation of Datasheet Parameters learly defined in the spec how to specify a clamping voltage for esd devices at the device level. ON Semiconductor has developed a way ESD Voltage Clamping to examine the entire voltage waveform across the ESd For sensitive circuit elements it is important to limit the protection diode over the time domain of an ESd pulse in the voltage that an IC will be exposed to during an ESd event form of an oscilloscope screenshot, which can be found on to as low a voltage as possible. The esd clamping voltage the datasheets for all esd protection diodes. For more is the voltage drop across the Esd protection diode during information on how on semiconductor creates these an esd event per the iec61000-4-2 waveform. Since the screenshots and how to interpret them please refer to IEC61000-4-2 was written as a pass/fail spec for larger AND8307/D 100 PEAK VALUE IRSM@8 us 山80 PULSE WIDTH (tp)IS DEFINED AS THAT POINT WHERE THE Ou0 70 PEAK CURRENT DECAY =8 us HALF VALUE IRSM/2 20 us 50 nSuLo8 40 30 10 0 80 t,TIME(us) Figure 5.8x 20 us Pulse Waveform http://onsemi.com 3 NUP2114UCMR6 Tektronix 划w[日1上p,国k eReftc7 E8) DE 197 my aF00pmn画图 Figure 6. 500 MHZ Data Pattern http://onsemi.co NUP2114UCMR6 PACKAGE DIMENSIONS TSOP-6 CASE 318G-02 SSUE U NOTE 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M. 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL 4 DIMENSIONS D AND E1 DO NOT INGLUDE MOLD FLASH GA PROTRUSIONS, OR GATE BURRS MOLD FLASH PROTRUSIONS OR E PLA GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H 5 PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE M SEATING MILLIMETERS NOTE 5 PLANE MAX DETAIL Z 0060.10 0100.180.26 90 c山A 50 70 085095 05 A1 0.60 DETAIL Z 0.25BSC RECOMMENDED SOLDERING FOOTPRINT 0.60 3.20 6X PITCH DIMENSIONS: MILLIMETERS For additional information on our Pb-Free strategy and soldering details, please download the on Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D ON Semiconductor and () arc registered trademarks of Semiconductor Components Industrics, LLC (SCILLC). SCILLC reserves the right to make changos without further notico Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Al operating parameters, including "Typicals" must be validated for each customer applicatian by customer's technical experts. SCILLC does not convey any license under its patent ngts nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant in o the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLc oroduct could create a situation where personal injury or death may occur. Should Buyer purchase or use SCiLLC products for any such unintended or unauthorized application, Buyer shall indemnify anc hold Scillc and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N.AmericanTechnicalSupport800-282-9855TollFreeOnSemiconductorWebsitewww.onseml.com Literature Distribution Center for oN Semiconductor USA/Canada PO. Box 5163. Denver Colorado 80217 USA Europe, Middle East and Africa Technical Support: OrderLiterature:http://www.onsemi.com/orderlit Phone: 303-675-2175 or 800-344-3860 Toll Free USA Canada Phone: 421 33790 2910 Fax: 303-675-2176 or B00-344-3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email:orderlit@onsemi.com Phone:81-3-5773-3850 Sales Representative NUP2114UCMR6/D