JEDEC Standard No. 305-R4-RCB
Version 1.0
-i-
DDR5 RDIMM STANDARD ANNEX B
Contents
Page
1 Scope ................................................................................................................................................. 1
2 DDR5 Registered DIMM Design File .............................................................................................. 1
3 Module Configuration ....................................................................................................................... 1
4 SDRAM Configuration ..................................................................................................................... 2
5 Supported Speeds .............................................................................................................................. 2
6 Design Deviations ............................................................................................................................. 2
7 General Layout .................................................................................................................................. 3
8 Functional Block Diagram ................................................................................................................ 4
9 SMBus Net Structures ....................................................................................................................... 8
10 Clock Input Net Structure ................................................................................................................. 8
11 Register Clock Output Net Structure ................................................................................................ 9
12 Data Net Structure – DQ, CB, DQS_t, DQS_c ............................................................................... 11
13 Post Register Address and Command Net Structure Routing ......................................................... 13
14 Post Register Control Net Structure Routing .................................................................................. 14
15 Pre-Register Address, Command’ and Parity Net Structure Routing .............................................. 15
16 DIMM Impedance Profile ............................................................................................................... 16
17 ALERT_n Output Net Structure Routing ........................................................................................ 17
18 DERROR_in_n Net Structure Routing ........................................................................................... 17
19 RESET_n and QRST_n Net Structure Routing .............................................................................. 18
20 Function Control Word Programming ............................................................................................. 19
21 Cross Section Recommendations .................................................................................................... 20
Tables
Table 1 — DDR5 Registered DIMM Design File ............................................................................................... 1
Table 2 — Module Configuration ................................................................................................
........................ 1
Table 3 — SDRAM Configuration ...................................................................................................................... 2
Table 4 — Supported Speeds ............................................................................................................................... 2
Table 5 — Design Deviations .............................................................................................................................. 2
Table 6 — SMBus Net Structures ........................................................................................................................ 8
Table 7 — Clock Lengths for Register Input Net Structures ............................................................................... 8
Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:18 am PDT
JEDEC
