JEDEC Standard No. 305-R8-RCE
Version 1.0
-i-
DDR5 RDIMM STANDARD ANNEX E
Contents
Page
1 Scope ................................................................................................................................................. 1
2 DDR5 Registered DIMM Design File .............................................................................................. 1
3 Module Configuration ....................................................................................................................... 1
4 SDRAM Configuration ..................................................................................................................... 2
5 Supported Speeds .............................................................................................................................. 2
6 Design Deviations ............................................................................................................................. 2
7 General Layout .................................................................................................................................. 3
8 Functional Block Diagram ................................................................................................................ 4
9 SMBus Net Structures ....................................................................................................................... 8
10 Clock Input Net Structure ................................................................................................................. 8
11 Register Clock Output Net Structure ................................................................................................ 9
12 Data Net Structure – DQ, CB, DQS_t, and DQS_c ........................................................................ 10
13 Post Register Address and Command Net Structure Routing ......................................................... 12
14 Post Register Control Net Structure Routing .................................................................................. 13
15 Pre-Register Address, Command, Control, and Parity Net Structure Routing ............................... 14
16 DIMM Impedance Profile ............................................................................................................... 15
17 RESET_n and QRST_n Net Structure Routing .............................................................................. 16
18 ALERT_n Output Net Structure Routing ........................................................................................ 16
19 DERROR_in_n Net Structure Routing ........................................................................................... 17
20 Function Control Word Programming............................................................................................. 18
21 Cross Section Recommendations .................................................................................................... 19
Tables
Table 1 — DDR5 Registered DIMM Design File ............................................................................................... 1
Table 2 — Module Configuration ........................................................................................................................ 1
Table 3 — SDRAM Configuration ...................................................................................................................... 2
Table 4 — Supported Speeds ............................................................................................................................... 2
Table 5 — Design Deviations .............................................................................................................................. 2
Table 6 — SMBus Net Structures ........................................................................................................................ 8
Table 7 — Clock Lengths for Register Input Net Structures ............................................................................... 8
Table 8 — Trace Lengths for Register Clock Output to SDRAM Load Net Structures ...................................... 9
JEDEC
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2022-11-28
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