JEDEC Standard No. 305-R8-RCD
Version 1.0
-i-
DDR5 RDIMM STANDARD ANNEX D
Contents
Page
1 Scope ................................................................................................................................................. 1
2 DDR5 Registered DIMM Design File .............................................................................................. 1
3 Module Configuration ....................................................................................................................... 1
4 SDRAM Configuration ..................................................................................................................... 2
5 Supported Speeds .............................................................................................................................. 2
6 Design Deviations ............................................................................................................................. 2
7 General Layout .................................................................................................................................. 3
8 Functional Block Diagram ................................................................................................................ 4
9 SMBus Net Structures ....................................................................................................................... 7
10 Clock Input Net Structure ................................................................................................................. 7
11 Register Clock Output Net Structure ................................................................................................ 8
12 Data Net Structure – DQ, CB, DQS_t, DQS_c ................................................................................. 9
13 Post Register Address and Command Net Structure Routing ......................................................... 11
14 Post Register Control Net Structure Routing .................................................................................. 12
15 Pre-Register Address, Command, and Parity Net Structure Routing .............................................. 13
16 DIMM Impedance Profile ............................................................................................................... 14
17 RESET_n and QRST_n Net Structure Routing .............................................................................. 15
18 ALERT_n Output Net Structure Routing ........................................................................................ 15
19 DERROR_in_n Net Structure Routing ........................................................................................... 16
20 Function Control Word Programming............................................................................................. 17
21 Cross Section Recommendations .................................................................................................... 18
Tables
Table 1 — DDR5 Registered DIMM Design File ............................................................................................... 1
Table 2 — Module Configuration ........................................................................................................................ 1
Table 3 — SDRAM Configuration ...................................................................................................................... 2
Table 4 — Supported Speeds ............................................................................................................................... 2
Table 5 — Design Deviations .............................................................................................................................. 2
Table 6 — SMBus Net Structures ........................................................................................................................ 7
Table 7 — Clock Lengths for Register Input Net Structures ............................................................................... 7
Table 8 — Trace Lengths for Register Clock Output to SDRAM Load Net Structures ...................................... 8
JEDEC
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