JESD305-R4-RCB_v1.02022DDR5RDIMMStandardAnnexB.pdf

版权申诉

JEDEC

5星 · 超过95%的资源 130 浏览量 2022-06-13 16:46:59 上传评论收藏 915KB PDF 举报

资源详情

资源评论

JEDEC

STANDARD

DDR5 RDIMM Standard Annex B

JESD305-R4-RCB

Version 1.0

APRIL 2022

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:18 am PDT

JEDEC

NOTICE

JEDEC standards and publications contain material that has been prepared, reviewed, and approved

through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC

legal counsel.

JEDEC standards and publications are designed to serve the public interest through eliminating

misunderstandings between manufacturers and purchasers, facilitating interchangeability and

improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the

proper product for use by those other than JEDEC members, whether the standard is to be used either

domestically or internationally.

JEDEC standards and publications are adopted without regard to whether or not their adoption may

involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to

any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or

publications.

The information included in JEDEC standards and publications represents a sound approach to product

specification and application, principally from the solid state device manufacturer viewpoint. Within the

JEDEC organization there are procedures whereby a JEDEC standard or publication may be further

processed and ultimately become an ANSI standard.

No claims to be in conformance with this standard may be made unless all requirements stated in the

standard are met.

Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should

be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents

for alternative contact information.

Published by

©JEDEC Solid State Technology Association 2022

3103 North 10th Street

Suite 240 South

Arlington, VA 22201-2108

JEDEC retains the copyright on this material. By downloading this file the individual agrees not to

charge for or resell the resulting material.

PRICE: Contact JEDEC

Printed in the U.S.A.

Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:18 am PDT

JEDEC

JEDEC Standard No. 305-R4-RCB

Version 1.0

-i-

DDR5 RDIMM STANDARD ANNEX B

Contents

Page

1 Scope ................................................................................................................................................. 1

2 DDR5 Registered DIMM Design File .............................................................................................. 1

3 Module Configuration ....................................................................................................................... 1

4 SDRAM Configuration ..................................................................................................................... 2

5 Supported Speeds .............................................................................................................................. 2

6 Design Deviations ............................................................................................................................. 2

7 General Layout .................................................................................................................................. 3

8 Functional Block Diagram ................................................................................................................ 4

9 SMBus Net Structures ....................................................................................................................... 8

10 Clock Input Net Structure ................................................................................................................. 8

11 Register Clock Output Net Structure ................................................................................................ 9

12 Data Net Structure – DQ, CB, DQS_t, DQS_c ............................................................................... 11

13 Post Register Address and Command Net Structure Routing ......................................................... 13

14 Post Register Control Net Structure Routing .................................................................................. 14

15 Pre-Register Address, Command’ and Parity Net Structure Routing .............................................. 15

16 DIMM Impedance Profile ............................................................................................................... 16

17 ALERT_n Output Net Structure Routing ........................................................................................ 17

18 DERROR_in_n Net Structure Routing ........................................................................................... 17

19 RESET_n and QRST_n Net Structure Routing .............................................................................. 18

20 Function Control Word Programming ............................................................................................. 19

21 Cross Section Recommendations .................................................................................................... 20

Tables

Table 1 — DDR5 Registered DIMM Design File ............................................................................................... 1

Table 2 — Module Configuration ................................................................................................

........................ 1

Table 3 — SDRAM Configuration ...................................................................................................................... 2

Table 4 — Supported Speeds ............................................................................................................................... 2

Table 5 — Design Deviations .............................................................................................................................. 2

Table 6 — SMBus Net Structures ........................................................................................................................ 8

Table 7 — Clock Lengths for Register Input Net Structures ............................................................................... 8

Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:18 am PDT

JEDEC