JEDEC Standard No. 308-U0-RCB
-i-
DDR5 UDIMM Raw Card Annex B
Contents
Page
1 Scope ................................................................................................................................................. 1
2 DDR5 Unbuffered DIMM Design File ............................................................................................. 1
3 Module Configuration ....................................................................................................................... 1
4 SDRAM Configuration ..................................................................................................................... 2
5 Supported Speeds .............................................................................................................................. 2
6 Design Deviations ............................................................................................................................. 2
7 General Layout .................................................................................................................................. 3
8 Functional Block Diagram ................................................................................................................ 4
9 SMBus Net Structure ........................................................................................................................ 7
10 Clock Net Structure ........................................................................................................................... 8
11 Data Net Structure – DQ, DM, CB, DQS_t, DQS_c ........................................................................ 9
12 Address and Command Net Structure Routing ............................................................................... 10
13 Control Net Structure Routing ........................................................................................................ 11
14 DIMM Impedance Profile ............................................................................................................... 12
15 RESET_n Net Structure Routing .................................................................................................... 13
16 ALERT_n Net Structure Routing .................................................................................................... 14
17 Cross Section Recommendations .................................................................................................... 15
Tables
Table 1 — DDR5 UDIMM Design File ........................................................................................................ 1
Table 2 — Module Configuration ................................................................................................................. 1
Table 3 — SDRAM Configuration ............................................................................................................... 2
Table 4 — Supported Speeds ........................................................................................................................ 2
Table 5 — Design Deviations ....................................................................................................................... 2
Table 6 — SMBus Net Structure .................................................................................................................. 7
Table 7 — Trace Lengths for Clock to SDRAM Load Net Structures ......................................................... 8
Table 8 — Trace Lengths for DQ_A, DM_A_n, CB_A, DQS_t_A, DQS_c_A ........................................... 9
Table 9 — Trace Lengths for Address and Command Net Structures ........................................................ 10
Table 10 — Trace Lengths for Control Net Structures ............................................................................... 11
Table 11 — Voltage Operating Conditions ................................................................................................. 12
