JEDEC Standard No. 305
-i-
DDR5 LOAD REDUCED (LRDIMM) AND REGISTERED DUAL INLINE MEMORY MODULE
(RDIMM) COMMON SPECIFICATION
Contents
1 Product Description .............................................................................................................................. 1
1.1 Related Documents............................................................................................................................ 1
2 Environmental Requirements ............................................................................................................... 2
3 Connector Pinout and Signal Description ............................................................................................ 3
4 Power Details ....................................................................................................................................... 8
4.1 DIMM Voltage Requirements and Power-Up Sequence .................................................................. 8
4.2 Rules for PMIC Power-Up Sequence ................................................................................................ 8
4.3 Rules for PMIC Power Down Sequence ........................................................................................... 8
4.4 Rules for VDD and VDDQ Power Planes ............................................................................................ 8
5 Component Details ............................................................................................................................... 9
5.1 Component Types and Placement ...................................................................................................... 10
5.2 Bulk and Distributed Decoupling Capacitance Guidelines ................................................................ 11
6 DIMM Design Details ........................................................................................................................ 12
6.1 Signal Groups ..................................................................................................................................... 12
6.2 General Net Structure Routing Rules ................................................................................................. 13
6.2.1 Pre-RCD Address, Command and Control ..................................................................................... 15
6.2.2 Pre-RCD Clock ............................................................................................................................... 16
6.2.3 Post-RCD Clock, Control, Address and Command Groups ............................................................ 16
6.2.4 Post-RCD Address and Command Group ....................................................................................... 16
6.2.5 Post-RCD Clock and Control Groups ............................................................................................. 17
6.2.6 Pre-Data Buffer Data and Strobe Group (LRDIMM) ..................................................................... 18
6.2.7 Post-Data Buffer Data and Strobe Group (LRDIMM) .................................................................... 20
6.2.8 Data and Strobe Group (RDIMM) .................................................................................................. 21
6.3 Design Rules ...................................................................................................................................... 23
6.4 Impedance Targets ............................................................................................................................. 27
6.5 Rules for Compensation ..................................................................................................................... 27
6.5.1 Velocity ........................................................................................................................................... 27
6.5.2 Via ................................................................................................................................................... 27
6.6 Rules for Length Calculation ............................................................................................................. 28
6.6.1 Pre-RCD and DQ/Strobe ................................................................................................................. 28
6.6.2 Pre-DB (LRDIMM) ......................................................................................................................... 28
6.6.3 Post-DB (LRDIMM) ....................................................................................................................... 28
6.6.4 Pre-RCD Clock ............................................................................................................................... 28
6.6.5 Post-RCD Address/Command/Control/Clock ................................................................................. 28
6.7 Rules for Registered and Load Reduced DIMM Designs .................................................................. 28
6.8 DQ Wiring to Support CRC ............................................................................................................... 29
6.9 RDIMM and LRDIMM Configuration .............................................................................................. 30
6.9.1 DIMM Connectivity Wiring ............................................................................................................ 30
6.9.2 Control Wiring ................................................................................................................................ 31
6.9.3 ALERT_n Circuit Wiring ................................................................................................................ 31
6.9.4 RESET_n Circuit Wiring ................................................................................................................ 32
6.10 ZQ Calibration Wiring .................................................................................................................... 32
6.11 Sideband Bus Signal Wiring, Selection and Placement .................................................................. 33
7 DIMM Impedance Profile .................................................................................................................. 34
8 Reference Stackup .............................................................................................................................. 35
9 Manufactured DIMMs ........................................................................................................................ 37
JEDEC
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