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JSSC 2023.8 all papers
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JSSC 2023.8 all papers
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AUGUST 2023 VOLUME 58
NUMBER 8
IJSCBC
(ISSN 0018-9200)
EDITORIALS
New Associate Editor ........................................................... . . . . . . . . . ............................. D. Sylvester 2127
New Associate Editor ... . . . . . . . . . ............................................... . . . . . . . . . ............................. D. Sylvester 2128
REGULAR PAPERS
A Study of Injection Locking in Oscillators and Frequency Dividers ... . . . . . . . . . .............. H. Razavi and B. Razavi 2129
A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation ........... O. Memioglu, Y. Zhao, and B. Razavi 2141
A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station Applications ... . . . . . . . . . .....
... . . . . . . . . ................................................ . . . . M. A. Montazerolghaem, L. C. N. de Vreede, and M. Babaie 2157
A 120-GHz Class-F Frequency Doubler With 7.8-dBm P
OUT
in 55-nm Bulk CMOS ..................... . . . . . . . . . .......
... . . . . . . . . . ............................................... . . . . . . . . . ....................... Z. Yang, K. Ma, F. Meng, and B. Liu 2173
Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS .... . . . . . . . . . .............................
... . . . . . . . . ........................ J. Nguyen, K. Khalaf, X. Tang, S. Brebels, K. Vaesen, M. Shrivas, and P. Wambacq 2189
A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength .. . ...............
... . . . . . . . . . ........................................... A. H. Ahmed, L. Vera, L. Iotti, R. Shi, S. Shekhar, and A. Rylyakov 2202
A Predistortion-Less Digital MIMO Transmitter With DTC-Based Quadrature Imbalance Compensation . .............
... . . . . . . . . . ............................................... . . . . . . . . . .................... J. Zanen, E. Klumperink, and B. Nauta 2214
A 100-to-10-kHz 5.4-to-216-µW Power-Efficient Readout Circuit Employing Closed-Loop Dynamic Amplifier for
MEMS Capacitive Accelerometer ..................................... L. Zhong, S. Liu, P. Shang, W. Cao, and Z. Zhu 2226
A 1.1- / 0.9-nA Temperature-Independent 213- /565-ppm/
◦
C Self-Biased CMOS-Only Current Reference in 65-nm
Bulk and 22-nm FDSOI ................................... . . . . . . . . . ................. M. Lefebvre, D. Flandre, and D. Bol 2239
(Contents Continued on Back Cover)
IEEE JOURNAL OF SOLID-STATE CIRCUITS
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Texas Instruments
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Nvidia
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Korea University
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Panasonic
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Intel
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University of Tokyo
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Imperial College London
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Intel
Portland, OR
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Intel
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Korea Advanced Institute of
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Sony
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IBM
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Indian Institute of
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D
ENNIS SYLVESTER,EDITOR-IN-CHIEF
Dept. Electr. Eng. Comput. Sci.
Univ. Michigan
Ann Arbor, MI 48109-2122
jssc.eic.sylvester@gmail.com
Associate Editors
M.-F. (MARVIN)CHANG
Department of Electrical
Engineering
National Tsing Hua
University (NTHU)
Hsinchu, Taiwan
mfchang@ee.nthu.edu.tw
J. C
HOI
School of Electrical Engineering
KAIST
Korea
jaehyouk@kaist.ac.kr
Y. D
ONG
MediaTek Inc.
Woburn, MA 01801, USA
yunzhi.dong@ieee.org
D. F
RIEDMAN
IBM T. J. Watson Research Center
Yorktown Heights, NY 10598, USA
dfriedmn@us.ibm.com
M. F
UJISHIMA
Graduate Sch. of
Adv. Science & Eng.
Hiroshima University
Japan
fuji@hiroshima-u.ac.jp
P. H
EYDARI
UC Irvine
Irvine, CA 92697, USA
jssc.heydari@gmail.com
T. J
ANG
Institute of Integrated Systems
ETH Zurich
Switzerland
tkjang@ethz.ch
W. H. K
I
Dept. Electronic Comp. Eng.
HKUST
Hong Kong, China
eeki@ust.hk
J. K
IM
Seoul National University
Seoul, Republic of Korea
jaeha@snu.ac.kr
H. L
EE
Department of Electrical and
Computer Engineering
University of Texas at Dallas
USA
hoilee@utdallas.edu
P.-I. M
AK
State Key Lab of
Analog & Mixed-Signal VLSI
Univ. of Macau
Macau, China
pimak@umac.mo
P. M
ALCOVATI
Univ. of Pavia
27100 Pavia, Italy
piero.malcovati@unipv.it
S. M
ATTHEW
Intel Corp.
USA
sanu.k.mathew@intel.com
H. P
AN
Broadcom Limited
Irvine, CA 92618 USA
hui.pan@broadcom.com
S. P
AVA N
Dept. Electr. Eng.
Indian Institute of Technology,
Madras
Chennai, India 600 036
shanthi@ee.iitm.ac.in
P. R
EYNAERT
KU Leuven ESAT-MICAS
Leuven, B3001, Belgium
patrick.reynaert@kuleuven.be
B. S
ADHU
IBM T. J. Watson Research Center
Yorktown Heights, NY 10598, USA
sadhu@us.ibm.com
D
R.N.A.W.DUTTON
STMichroelectronics
Edinburgh, U.K.
neale.dutton@st.com
N. V
AN HELLEPUTTE
Systems & Circuits for
Connected Health
IMECbe
Leuven I Belgium
Nick.VanHelleputte@imec.be
K. W
ILCOX
AMD
Boxborough, MA, USA
Kathy.wilcox@amd.com
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Dig
ital Object Identifier 10.1109/JSSC.2023.3291192
AUGUST 2023 VOLUME 58
NUMBER 8
IJSCBC
(ISSN 0018-9200)
EDITORIALS
New Associate Editor ... . . . . . . . . . ................................................. . . . . . . . . . ........................... D. Sylvester 2127
New Associate Editor ... . . . . . . . . . ................................................. . . . . . . . . . ........................... D. Sylvester 2128
REGULAR PAPERS
A Study of Injection Locking in Oscillators and Frequency Dividers ..... . . . . . . . .............. H. Razavi and B. Razavi 2129
A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation ........... O. Memioglu, Y. Zhao, and B. Razavi 2141
A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station Applications ..... . . . . . . . . . ...
... . . . . . . . . .................................................. . . M. A. Montazerolghaem, L. C. N. de Vreede, and M. Babaie 2157
A 120-GHz Class-F Frequency Doubler With 7.8-dBm P
OUT
in 55-nm Bulk CMOS ......................... . . . . . . . . . ...
... . . . . . . . . . ................................................. . . . . . . . . . ..................... Z. Yang, K. Ma, F. Meng, and B. Liu 2173
Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS ........ . . . . . . . . . .........................
... . . . . . . . . ........................ J. Nguyen, K. Khalaf, X. Tang, S. Brebels, K. Vaesen, M. Shrivas, and P. Wambacq 2189
A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength .. . ...............
... . . . . . . . . . ........................................... A. H. Ahmed, L. Vera, L. Iotti, R. Shi, S. Shekhar, and A. Rylyakov 2202
A Predistortion-Less Digital MIMO Transmitter With DTC-Based Quadrature Imbalance Compensation . .............
... . . . . . . . . . ................................................. . . . . . . . . . .................. J. Zanen, E. Klumperink, and B. Nauta 2214
A 100-to-10-kHz 5.4-to-216-µW Power-Efficient Readout Circuit Employing Closed-Loop Dynamic Amplifier for
MEMS Capacitive Accelerometer ..................................... L. Zhong, S. Liu, P. Shang, W. Cao, and Z. Zhu 2226
A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/
◦
C Self-Biased CMOS-Only Current Reference in 65-nm
Bulk and 22-nm FDSOI ................................... . . . . . . . . . ................. M. Lefebvre, D. Flandre, and D. Bol 2239
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms
Jitter PLL ............................... . . . Y. Wang, J. Shi, H. Xu, S. Ji, Y. Mao, T. Zou, J. Tao, H. Min, and N. Yan 2252
Low-Power Process and Temperature-Invariant Constant Slope-and-Swing Ramp-Based Phase Interpolator ...........
... . . . . . . . . .................................................. . . . . . . . . . ........ S. Mohapatra, C.-C. Lin, S. Gupta, and D. Heo 2267
Spatially Resolved Event-Driven 24 × 24 Pixels SPAD Imager With 100% Duty Cycle for Low Optical Power
Quantum Entanglement Detection ......................... . . . . . . . . . ................................................. . . . . . . . . . ...
... . . . . . . . . ......... F. Severini, I. Cusini, F. Madonini, D. Brescia, R. Camphausen, Á. Cuevas, S. Tisa, and F. Villa 2278
An 18-MS/s 76-dB SNDR Continuous-Time 16 Modulator Incorporating an Input Voltage Tracking GmC Loop
Filter ....................................... . . . . . . . . . ........ M. Runge, J. Edler, T. Kaiser, K. Misselwitz, and F. Gerfers 2288
A 38-GS/s 7-bit Pipelined-SAR ADC With Speed-Enhanced Bootstrapped Switch and Output Level Shifting Technique
in 22-nm FinFET ........................................ . . . . . . . . ................................................ . . . . . . . . . .........
... . . . . . . . . ...... Y. Zhu, T. Liu, S. K. Kaile, S. Kiran, I.-M. Yi, R. Liu, J. C. Gomez Diaz, S. Hoyos, and S. Palermo 2300
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain
Decision Technique for Multi-Chip Module Memory Interfaces .................... . . . . . . . .................................
... . . . . . . . . . ...... Y. Kwon, H. Park, Y. Choi, J. Sim, J. Choi, S. Park, K.-M. Kim, C. Choi, H.-K. Jung, and C. Kim 2314
A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for
High-Density Interconnects ... . . . . . . . . . .................................................. . . . . . . . . Q. Liu, L. Du, and Y. Du 2326
Fully Integrated Frequency-Tuning Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting . . . . . . . . . .........
... . . . . . . . . .................................................. . . . . . . . . . .... C. Xie, G. Zhao, Y. Ma, M.-K. Law, and M. Zhang 2337
A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable
Delay Range and 330 ns/mm
2
Area Efficiency ........................................... . . . . . . . . . ...........................
.. . . . . . . . . . .................................... T. Forbes, B. Magstadt, J. Moody, J. Saugen, A. Suchanek, and S. Nelson 2349
TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme
Edge ..................... . . . . . . . . . ................. V. Jain, S. Giraldo, J. De Roose, L. Mei, B. Boons, and M. Verhelst 2360
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array ..........................
... . . . . . . . . .................................................. . C. Yu, J. Mu, Y. Su, K. T. C. Chai, T. T.-H. Kim, and B. Kim 2372
A 334 µW 0.158 mm
2
ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding
Toom–Cook Multiplication ... . . . . . . . . ................................................ . . . . . . . . . ...................................
... . . . . . . . . .................... A. Ghosh, J. M. B. Mera, A. Karmakar, D. Das, S. Ghosh, I. Verbauwhede, and S. Sen 2383
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 58, NO. 8, AUGUST 2023 2127
New Associate Editor
I
T IS with great pleasure that I welcome Dr. Ben Keller
to the editorial board of the IEEE JOURNAL OF SOLID-
STATE CIRCUITS as a new Associate Editor. Dr. Keller is
an expert on digital circuits, processor design, and machine
learning accelerators.
Digital Object Identifier 10.1109/JSSC.2023.3291827
DENNIS SYLVESTER, Editor-in-Chief
University of Michigan
Ann Arbor, MI 48109 USA
e-mail: jssc.eic.sylvester@gmail.com
Ben Keller (Member, IEEE) received the B.S. degree in engineering from Harvey Mudd College,
Claremont, CA, USA, in 2010, and the M.S. and Ph.D. degrees in electrical engineering and
computer sciences from the University of California at Berkeley, Berkeley, CA, USA, in 2015
and 2017, respectively.
He joined the ASIC&VLSI Research Group at NVIDIA, Inc., Santa Clara, CA, USA, in 2017,
where he works as a Senior Research Scientist. His research interests include digital clocking and
synchronization techniques, hardware design productivity, and energy-efficient neural network
inference.
Dr. Keller has served previously for the DATE Technical Program Committee.
0018-9200 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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