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JULY 2023

VOLUME 58

NUMBER 7

IJSCBC

(ISSN 0018-9200)

SPECIAL ISSUE ON IEEE 2022 EUROPEAN SOLID-STATE CURCUITS CONFERENCE

GUEST EDITORIAL

IEEE 2022 European Solid-State Circuits Conference ........................................... M. Nagata and M. Alioto 1823

SPECIAL ISSUE PAPERS

An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA

With 4.5-dB NF and 11.5-dBm OIP3 ............................. . . C. Chen, D. Huang, Y. Zhao, Y. Jin, and J. Yang 1825

A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging ....... D. Krüger,

A. Zhang, B. Aghelnejad, H. Hinton, V. M. Arnal, Y.-Q. Song, Y. Tang, K.-M. Lei, J. Anders, and D. Ham 1838

A 4–40 V Wide Input Range Boost Converter With the Protection Re-Cycling Technique for 200 W High Power

LiDAR System in a Long-Distance Object Detection ................................... . . . . . . . . . ............................

... . . . . S.-Y. Li, S. C. Lee, S.-H. Hung, Z.-L. Huang, K.-H. Chen, K.-L. Zheng, Y.-H. Lin, S.-R. Lin, and T.-Y. Tsai 1850

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration

of IoT Devices .... . . . S. Lim, Y. Goh, Y. K. Lee, D. H. Ko, J. Hwang, Y. Jeong, H. Shin, S. Jeon, and S.-O. Jung 1860

IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W

146-TOPS/mm

CIM-SRAM With Multi-Bit Analog Batch-Normalization ..............................................

... . . . . . . . . ................................................ . . . . . . . . . ........... A. Kneip, M. Lefebvre, J. Verecken, and D. Bol 1871

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured

Sparsity ...................... . . . . . . . . . ................................................ . . . . . . . . . ....... S. K. Venkataramanaiah,

J. Meng, H.-S. Suh, I. Yeo, J. Saikia, S. K. Cherupally, Y. Zhang, Z. Zhang, and J.-S. Seo 1885

REGULAR PAPERS

A Reconﬁgurable Phase-Time Array Transmitter Achieving Keyless Secured Transmission and Multi-Receiver

Localization for Low-Latency Joint Communication and Sensing ............................. . . . . . . . . . ....................

... . . . . . . . . ................................................ . N. S. Mannem, J. Park, E. Erfani, E. Liu, J. Lee, and H. Wang 1898

A 220-GHz Sliding-IF Quadrature Transmitter and Receiver Chipset for High Data Rate Communication in 0.13-µm

SiGe BiCMOS ......... . . . . . . . . . .................. Z. Li, J. Chen, H. Li, J. Yu, Y. Lu, R. Zhou, Z. Chen, and W. Hong 1913

(Contents Continued on Back Cover)

IEEE JOURNAL OF SOLID-STATE CIRCUITS

The IEEE JOURNAL OF SOLID-STATE CIRCUITS is published by the IEEE Solid-State Circuits Society. For membership and subscription information and pricing, please visit

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ULLER

University of California, Berkeley

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Korea University

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Panasonic

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AHONY

Intel

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University of Tokyo

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Imperial College London

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Intel

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C. T

OKUNAGA

Intel

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Korea Advanced Institute of

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Sony

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IBM

STANDING COMMITTEE CHAIRS

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Intel Corporation

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EDITOR

ENNIS SYLVESTER,EDITOR-IN-CHIEF

Dept. Electr. Eng. Comput. Sci.

Univ. Michigan

Ann Arbor, MI 48109-2122

jssc.eic.sylvester@gmail.com

Associate Editors

M.-F. (MARVIN)CHANG

Department of Electrical

Engineering

National Tsing Hua

University (NTHU)

Hsinchu, Taiwan

mfchang@ee.nthu.edu.tw

J. C

HOI

School of Electrical Engineering

KAIST

Korea

jaehyouk@kaist.ac.kr

Y. D

ONG

MediaTek Inc.

Woburn, MA 01801, USA

yunzhi.dong@ieee.org

D. F

RIEDMAN

IBM T. J. Watson Research Center

Yorktown Heights, NY 10598, USA

dfriedmn@us.ibm.com

M. F

UJISHIMA

Graduate Sch. of

Adv. Science & Eng.

Hiroshima University

Japan

fuji@hiroshima-u.ac.jp

P. H

EYDARI

UC Irvine

Irvine, CA 92697, USA

jssc.heydari@gmail.com

T. J

ANG

Institute of Integrated Systems

ETH Zurich

Switzerland

tkjang@ethz.ch

W. H. K

Dept. Electronic Comp. Eng.

HKUST

Hong Kong, China

eeki@ust.hk

J. K

Seoul National University

Seoul, Republic of Korea

jaeha@snu.ac.kr

H. L

Department of Electrical and

Computer Engineering

University of Texas at Dallas

USA

hoilee@utdallas.edu

P.-I. M

State Key Lab of

Analog & Mixed-Signal VLSI

Univ. of Macau

Macau, China

pimak@umac.mo

P. M

ALCOVATI

Univ. of Pavia

27100 Pavia, Italy

piero.malcovati@unipv.it

S. M

ATTHEW

Intel Corp.

USA

sanu.k.mathew@intel.com

H. P

Broadcom Limited

Irvine, CA 92618 USA

hui.pan@broadcom.com

S. P

AVA N

Dept. Electr. Eng.

Indian Institute of Technology,

Madras

Chennai, India 600 036

shanthi@ee.iitm.ac.in

P. R

EYNAERT

KU Leuven ESAT-MICAS

Leuven, B3001, Belgium

patrick.reynaert@kuleuven.be

B. S

ADHU

IBM T. J. Watson Research Center

Yorktown Heights, NY 10598, USA

sadhu@us.ibm.com

R.N.A.W.DUTTON

STMichroelectronics

Edinburgh, U.K.

neale.dutton@st.com

N. V

AN HELLEPUTTE

Systems & Circuits for

Connected Health

IMECbe

Leuven I Belgium

Nick.VanHelleputte@imec.be

K. W

ILCOX

AMD

Boxborough, MA, USA

Kathy.wilcox@amd.com

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Digital Object Identiﬁer 10.1109/JSSC.2023.3282830

JULY 2023

VOLUME 58

NUMBER 7

IJSCBC

(ISSN 0018-9200)

SPECIAL ISSUE ON IEEE 2022 EUROPEAN SOLID-STATE CURCUITS CONFERENCE

GUEST EDITORIAL

IEEE 2022 European Solid-State Circuits Conference ..... . . . . . . . ............................... M. Nagata and M. Alioto 1823

SPECIAL ISSUE PAPERS

An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA

With 4.5-dB NF and 11.5-dBm OIP3 ............................... C. Chen, D. Huang, Y. Zhao, Y. Jin, and J. Yang 1825

A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging ....... D. Krüger,

A. Zhang, B. Aghelnejad, H. Hinton, V. M. Arnal, Y.-Q. Song, Y. Tang, K.-M. Lei, J. Anders, and D. Ham 1838

A 4–40 V Wide Input Range Boost Converter With the Protection Re-Cycling Technique for 200 W High Power

LiDAR System in a Long-Distance Object Detection ..................................... . . . . . . . . . ..........................

... . . . . S.-Y. Li, S. C. Lee, S.-H. Hung, Z.-L. Huang, K.-H. Chen, K.-L. Zheng, Y.-H. Lin, S.-R. Lin, and T.-Y. Tsai 1850

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration

of IoT Devices .... . . . S. Lim, Y. Goh, Y. K. Lee, D. H. Ko, J. Hwang, Y. Jeong, H. Shin, S. Jeon, and S.-O. Jung 1860

IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W

146-TOPS/mm

CIM-SRAM With Multi-Bit Analog Batch-Normalization ..............................................

... . . . . . . . . .................................................. . . . . . . . . . ......... A. Kneip, M. Lefebvre, J. Verecken, and D. Bol 1871

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured

Sparsity ......................... . . . . . . .................................................. . . . . . . . . . ..... S. K. Venkataramanaiah,

J. Meng, H.-S. Suh, I. Yeo, J. Saikia, S. K. Cherupally, Y. Zhang, Z. Zhang, and J.-S. Seo 1885

REGULAR PAPERS

A Reconﬁgurable Phase-Time Array Transmitter Achieving Keyless Secured Transmission and Multi-Receiver

Localization for Low-Latency Joint Communication and Sensing ............................... . . . . . . . ....................

... . . . . . . . . ................................................. N. S. Mannem, J. Park, E. Erfani, E. Liu, J. Lee, and H. Wang 1898

A 220-GHz Sliding-IF Quadrature Transmitter and Receiver Chipset for High Data Rate Communication in 0.13-µm

SiGe BiCMOS ......... . . . . . . . . . .................. Z. Li, J. Chen, H. Li, J. Yu, Y. Lu, R. Zhou, Z. Chen, and W. Hong 1913

Digital to RF Wideband Multi-Standard Multi-Path Transmitter ..................... . . . . . . ....................................

... . . . . . . . . .................................................. . . . R. Ehsani Alashti, S. Mohin, F. Tavana, and M. S. Bakhtiar 1928

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise

and I/Q Exactness ...... . . . . . . . . ................. X. Chen, Y. Hu, T. Siriburanon, J. Du, R. B. Staszewski, and A. Zhu 1945

A Wideband Mode-Switching Quad-Core VCO Using Compact Multi-Mode Magnetically Coupled LC Network ....

... . . . . . . . . .................................................. . . . . . . . . . ......................... C. Li, J. Guo, P. Qin, and Q. Xue 1959

A Reﬂection-Mode N -Path Filter Tunable From 6 to 31 GHz .............. S. Hari, C. J. Ellington, and B. A. Floyd 1973

Chip-to-Chip Interfaces for Large-Scale Highly Conﬁgurable mmWave Phased Arrays ........ . . . . . . . . . ....... A. Sethi,

R. Akbar, M. Hietanen, J. P. Aikio, O. Kursu, M. Jokinen, M. E. Leinonen, T. Rahkonen, and A. Pärssinen 1987

A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory

Interfaces ......................... . Y. Choi, H. Park, J. Choi, J. Sim, Y. Kwon, S. Park, S. Kim, C. Sim, and C. Kim 2005

A 1-GS/s 6–8-b Cryo-CMOS SAR ADC for Quantum Computing .. . . . . ......................................... G. Kiene,

R. W. J. Overwater, A. Catania, A. G. Sreenivasulu, P. Bruschi, E. Charbon, M. Babaie, and F. Sebastiano 2016

A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm

Field of

View ............................. . . . . . . . . . ...................... S. Fan, Q. Zhou, K.-M. Lei, P.-I. Mak, and R. P. Martins 2028

A Baseline-Tracking Single-Channel I/Q Impedance Plethysmogram IC for Neckband-Based Blood Pressure and

Cardiovascular Monitoring ...... . . . . . . . . . ....... C. S. Park, H. Kim, K. Lee, D. S. Keum, D. P. Jang, and J. J. Kim 2040

A 1 mm × 1 mm CGM System on Die Achieving 1.65-nA/mM In Vivo Resolution and 0–40-mM/L Detection Range

With 16 Backscatter Technique .................................... . . . . . . . . . .................................................. .

... . . . . . . . . . ........... Z. Li, C. Yang, Y. Zhang, T.-H. Wang, Z. Chang, B. Zhu, L. Zhou, Y. Luo, B. Su, and B. Zhao 2053

A 1-µW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/

◦

C and Single-Point Trimmed 8.7-ppm/

◦

C Stability

From −40

◦

C to 95

◦

C ............................... . . . . . . .................................................. . . . . . . . . . ...........

... . . . . . . . . . ......... K.-S. Park, A. Khashaba, A. Abdelrahman, Y. Li, T. Wang, R. Xia, N. Pal, and P. K. Hanumolu 2064

A 7-nm FinFET 1.2-TB/s/mm

3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using

Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver ............................................ . . . . . . . . .

... . . . . . . . . .................................................. . K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda 2075

ASCH-PUF: A “Zero” Bit Error Rate CMOS Physically Unclonable Function With Dual-Mode Low-Cost

Stabilization ........... . . . . . . . . . .................................................. . . . . . . . . . .. Y. He, D. Li, Z. Yu, and K. Yang 2087

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline

Pulse Timing .......... . . . . . . . . . ............................. Y. Yokoyama, K. Nii, Y. Ishii, S. Tanaka, and K. Kobayashi 2098

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled

Precharge Eliminating DACs for Energy-Efﬁcient DNN Inference ................................. . . . . . . . .. ...............

... . . . . . . . . . ................................................. . . . . . . . . R. Sehgal, T. Thareja, S. Xie, C. Ni, and J. P. Kulkarni 2109

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 58, NO. 7, JULY 2023 1823

Guest Editorial

IEEE 2022 European Solid-State

Circuits Conference

HIS Special Section of the IEEE JOURNAL OF SOLID-

STATE CIRCUITS features expanded versions of selected

articles presented at the 2022 European Solid-State Circuits

Conference (ESSCRIC) that was held in Milan, Italy, during

September 19–22, 2022. The invited papers properly reﬂect

the conference theme of “Intelligent electronics for a smarter

and more inclusive human life.”

In [A1], Chen et al. present an ultra-low-voltage 2.4-GHz

RF receiver front-end architecture that intends to eliminate

the output ﬂicker noise and to deploy zero-IF topology in

narrow-band communication standards. The TIA in 28 nm RF

CMOS demonstrated a ﬂicker-noise-corner frequency of less

than 10 KHz.

In [A2], Kruger et al. present a small nuclear magnetic

resonance (NMR) system comprising a digitally assisted

CMOS RF transceiver IC and a 0.51-T permanent magnet

that achieves a record-high spectral resolution of <0.05 ppm

(1.1 Hz) and an imaging resolution of 67 × 67 × 83 µm

The contribution is followed by [A3] by Li et al.

A high-conversion ratio boost converter with protection recy-

cling for eGaN power FET transistors is introduced. The pro-

tection against Ldi/dt over-voltages simultaneously improves

the converter efﬁciency. The protection is applied to LiDAR

systems subject to large battery voltage ﬂuctuations at power-

on from 4 to 40 V.

In [A4], Lim et al. present a self-rectifying ferroelectric tun-

nel junction (SR-FTJ) crosspoint array that can operate in the

mode of ternary content-addressable memory (TCAM), binary

CAM (BCAM), or physically unclonable function (PUF).

The above work is then followed by the contribution [A5] by

Kneip et al. The compute-in-memory SRAM presented in this

work targets low-precision edge convolutional neural networks

(CNNs) and includes a 1-to-4-b mixed-signal accelerator based

and a multibit analog batch-normalization unit to mitigate

the effect of limited precision. The SRAM macro exhibits a

4b-normalized efﬁciency of 813 TOPS/W at 64 MHz.

The ﬁnal contribution is made by [A6] by Venkataramanaiah

et al. The article introduces an 8-bit ﬂoating-point training

processor with highly parallel tensor cores maintaining high

utilization across forward propagation, backward propagation,

Digital Object Identiﬁer 10.1109/JSSC.2023.3278008

and weight update. Improvements in FLOPs reduction (7.3× ),

energy efﬁciency (16.4 TFLOPS/W), and training latency

(4.7×) are shown in a 28-nm test chip under both supervised

and self-supervised training tasks.

We trust you will enjoy the Special Issue and the ﬁne

contributions that it comprises, in view of the expanded scope

beyond the well-received presentations at ESSCIRC.

MAKOTO NAGATA, Guest Editor

Graduate School of Science, Technology

and Innovation

Kobe University

Kobe 657-8501, Japan

MASSIMO ALIOTO, Guest Editor

Department of Electronics and

Communication Engineering

National University of Singapore

Singapore 117583

APPENDIX: RELATED ARTICLES

[A1] C. Chen, D. Huang, Y. Zhao, Y. Jin, and J. Yang, “An ultra-

low-voltage 2.4-GHz ﬂicker-noise-free RF receiver front end based

on switched-capacitor hybrid TIA with 4.5-dB NF and 11.5-dBm

OIP3,” IEEE J. Solid-State Circuits, early access, Apr. 24, 2023, doi:

10.1109/JSSC.2023.3266268.

[A2] D. Kruger et al., “A portable CMOS-based spin resonance system for

high-resolution spectroscopy and imaging,” IEEE J. Solid-State Cir-

cuits, early access, May 17, 2023, doi: 10.1109/JSSC.2023.3274043.

[A3] S. Li et al., “A 4–40 V wide input range boost converter with the

protection re-cycling technique for 200 W high power LiDAR system

in a long-distance object detection,” IEEE J. Solid-State Circuits, early

access, May 3, 2023, doi: 10.1109/JSSC.2023.3269026.

[A4] S. Lim et al., “Dual-mode operations of self rectifying ferroelectric

tunnel junction crosspoint array for high density integration of IoT

devices,” IEEE J. Solid-State Circuits, early access, Apr. 18, 2023,

doi: 10.1109/JSSC.2023.3265667.

[A5] A. Kneip, M. Lefebvre, J. Verecken, and D. Bol, “IMPACT: A 1-to-

4b 813-TOPS/W 22-nm FD-SOI compute-in-memory CNN accelerator

featuring a 4.2-POPS/W 146-TOPS/mm

CIM-SRAM with multi-bit

analog batch-normalization,” IEEE J. Solid-State Circuits, early access,

May 19, 2023, doi: 10.1109/JSSC.2023.3269098.

[A6] S. K. Venkataramanaiah et al., “A 28-nm 8-bit ﬂoating-point ten-

sor core-based programmable CNN training processor with dynamic

structured sparsity,” IEEE J. Solid-State Circuits, early access,

May 15, 2023, doi: 10.1109/JSSC.2023.3269148.

See https://www.ieee.org/publications/rights/index.html for more information.

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