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JSSC 2023.12 all papers
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DECEMBER 2023 VOLUME 58
NUMBER 12
IJSCBC
(ISSN 0018-9200)
SPECIAL SECTION ON THE 2023 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)
GUEST EDITORIAL
Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC) ........
................................................. J. F. Buckwalter, A. Zolfaghari, D. A. Hall, K.-H. Chen, and D. Morche 3291
SPECIAL SECTION PAPERS
A Transformer-Based Quadrature Doherty Digital Power Amplifier With 4.1 W Peak Power in 28 nm Bulk
CMOS . .............................. J. Li, Y. Yin, H. Chen, J. Lin, Y. Li, X. Jia, Z. Hu, Z. Liu, X. Zhang, and H. Xu 3296
Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust
Common-Mode Resonance ................................................................................ Y. Shu and X. Luo 3308
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive
Dithering ................................. . . . . . . . . . ................................................ . . . . . . . . ....... S. M. Dartizio,
F. Tesolin, G. Castoro, F. Buccoleri, M. Rossoni, D. Cherniak, C. Samori, A. L. Lacaita, and S. Levantino 3320
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a
Ring-VCO-Based Fractional-Resolution Frequency Multiplier ........................................... . . . . . . . ............
... . . . . . . . . . ............................................... . Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi 3338
A Third-Order Quasi-Elliptic N-Path Filter With Enhanced Linearity Through Clock Boosting . . . . . . . . . .................
.. . . . . . . . . . ......................................... A. Nagulu, Y. Zhuang, M. Yuan, S. Garikapati, and H. Krishnaswamy 3351
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET ... . .
... . . . . . . . . ................................................ . . . . . . . . . ........................ A. Agrawal, A. Whitcombe, W. Shin,
R. Bhat, S. Kundu, P. Sagazio, H. Chandrakumar, T. W. Brown, B. R. Carlton, C. Hull, S. Callender, and S. Pellerano 3364
A Low-Power 256-Element K a-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for
Small Satellite Constellations ......... . . . . . . . . ................................................ . . . . . . . . . ..........................
... . . . . . . . . . . X. Fu, D. You, X. Wang, Y. Wang, C. J. Mayeda, Y. Gao, M. Ide, Y. Zhang, J. Sakamaki, A. A. Fadila,
Z. Li, J. Sudo, M. Higaki, S. Inoue, T. Eishima, T. Tomura, J. Pang, H. Sakai, K. Okada, and A. Shirane 3380
(Contents Continued on Back Cover)
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School of Electrical Engineering
KAIST
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ONG
MediaTek Inc.
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UJISHIMA
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EYDARI
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NVIDIA Research
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Intel Corp.
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ALERMO
Texas A&M University
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AN
Broadcom Limited
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hui.pan@broadcom.com
S. P
AVA N
Dept. Electr. Eng.
Indian Institute of Technology,
Madras
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KU Leuven ESAT-MICAS
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Delft University of Technology
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Digital Object Identifier 10.1109/JSSC.2023.3332153
DECEMBER 2023 VOLUME 58
NUMBER 12
IJSCBC
(ISSN 0018-9200)
SPECIAL SECTION ON THE 2023 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)
GUEST EDITORIAL
Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC) ... . . . . .
... . . . . . . . . . ..................................... J. F. Buckwalter, A. Zolfaghari, D. A. Hall, K.-H. Chen, and D. Morche 3291
SPECIAL SECTION PAPERS
A Transformer-Based Quadrature Doherty Digital Power Amplifier With 4.1 W Peak Power in 28 nm Bulk
CMOS . .............................. J. Li, Y. Yin, H. Chen, J. Lin, Y. Li, X. Jia, Z. Hu, Z. Liu, X. Zhang, and H. Xu 3296
Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust
Common-Mode Resonance ................................................ . . . . . . . . . ....................... Y. Shu and X. Luo 3308
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive
Dithering ................................. . . . . . . . . . ................................................ . . . . . . . . ....... S. M. Dartizio,
F. Tesolin, G. Castoro, F. Buccoleri, M. Rossoni, D. Cherniak, C. Samori, A. L. Lacaita, and S. Levantino 3320
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a
Ring-VCO-Based Fractional-Resolution Frequency Multiplier ........................................... . . . . . . . . . ..........
... . . . . . . . . . ............................................... . Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi 3338
A Third-Order Quasi-Elliptic N-Path Filter With Enhanced Linearity Through Clock Boosting .. . . . . . ...................
.. . . . . . . . . . ......................................... A. Nagulu, Y. Zhuang, M. Yuan, S. Garikapati, and H. Krishnaswamy 3351
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET .....
... . . . . . . . . ................................................ . . . . . . . . . ........................ A. Agrawal, A. Whitcombe, W. Shin,
R. Bhat, S. Kundu, P. Sagazio, H. Chandrakumar, T. W. Brown, B. R. Carlton, C. Hull, S. Callender, and S. Pellerano 3364
A Low-Power 256-Element K a-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for
Small Satellite Constellations . . . . . . . . . ............................................... . . . . . . . . . ...................................
... . . . . . . . . . . X. Fu, D. You, X. Wang, Y. Wang, C. J. Mayeda, Y. Gao, M. Ide, Y. Zhang, J. Sakamaki, A. A. Fadila,
Z. Li, J. Sudo, M. Higaki, S. Inoue, T. Eishima, T. Tomura, J. Pang, H. Sakai, K. Okada, and A. Shirane 3380
Harmonic-Resilient Fully Passive Mixer-First Receiver for Software-Defined Radios ................................. . . . . .
... . . . . . . . . ................................................ . . . . . . . . . ................... S. Araei, S. Mohin, and N. Reiskarimian 3396
A Fully Integrated IEEE 802.15.4/4z-Compliant UWB System-on-Chip RF Transceiver Supporting Precision
Positioning in a CMOS 28-nm Process .................... . . . . . . . . . ............................................... . . . . . . . . . ....
... . . . . . . . . .......................... W. Kim, H.-G. Seok, G. Lee, S. Kim, J.-K. Lee, C. Kim, W. Kim, W. Jung, Y. Cho,
S. Bae, J. Cho, H. Na, B. Kang, H. Han, H. Son, S. Lee, D. Kim, J.-S. Paek, S. Oh, J. Lee, S. Kwak, and J. Kim 3408
A Highly Integrated Distributed Mixer Receiver for Low-Power Wireless Radios ........................ . . . . . . . . . .........
... . . . . . . . . ................................................ . . . . . . . . . .............. H. Bialek, M. L. Johnston, and A. Natarajan 3421
A Sub-1 V Capacitively Biased BJT-Based Temperature Sensor With an Inaccuracy of ±0.15
◦
C (3σ ) From −55
◦
C
to 125
◦
C ..... . . . . . . . . . ............................................... Z. Tang, S. Pan, M. Grubor, and K. A. A. Makinwa 3433
A Hybrid Magnetic Current Sensor With a Dual Differential DC Servo Loop ............. . . . . . . . . . ........................
... . . . . . . . . . ................................... A. Jouyaeian, Q. Fan, U. Ausserlechner, M. Motz, and K. A. A. Makinwa 3442
A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme ...................
... . . . . . . . . ................................................ . . . . . . . . . .. S. Pan, X. An, Z. Yu, H. Jiang, and K. A. A. Makinwa 3450
A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From −40
◦
C to 85
◦
C After
Accelerated Aging for 500 h at 125
◦
C . . ............................................... . . . . . . . . . ..............................
... . . . . . . . . . .......................... K.-S. Park, N. Pal, Y. Li, R. Xia, T. Wang, A. Abdelrahman, and P. K. Hanumolu 3459
A 120.9-dB DR Digital-Input Capacitively Coupled Chopper Class-D Audio Amplifier ............................. . . . . .
.. . . . . . . . . . ................................................ . . . . . . . . . . H. Zhang, M. Berkhout, K. A. A. Makinwa, and Q. Fan 3470
On-Chip Condition-Adaptive 1 f
3
EMI Control for Switching Power ICs .............. L. Du, D. Yan, and D. B. Ma 3481
A 12-to-1 V Quad-Output Switched-Capacitor Buck Converter With Shared DC Capacitors .......... . . . . . . . . . ..........
... . . . . . . . . ................................................ . . . . . . . . . ................ T. Hu, M. Huang, R. P. Martins, and Y. Lu 3492
A Reconfigurable Single-Inductor Multi-Stage Hybrid Converter for 1-Cell Battery Chargers ... . . . . . . . . . ...............
... . . . . . . . . . ............................................... . . . . . . . . . ........................................ C. Hardy and H.-P. Le 3503
A Scalable N -Step Equally Split SSHI Rectifier for Piezoelectric Energy Harvesting With Low-Q Inductor ..........
... . . . . . . . . . ............................................... . . . . . . . . . ....................... Y.-W. Jeong, S.-J. Lee and S.-U. Shin 3519
A Modular Switched-Capacitor Chip-Stacking Drive Platform for kV-Level Electrostatic Actuators .. . . ................
... . . . . . . . . . ............................................... . . . . . . . . . ......................... Y. Li, B. Mabetha, and J. T. Stauth 3530
A Three-Level Boost Converter With Fully State-Based Phase Selection Technique for High-Speed V
CF
Calibration
and Smooth Mode Transition .................... . . . . . . . . . ......................... S.-J. Lee, Y.-W. Jeong, and S.-U. Shin 3544
A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive
Level-Shifting . . . . . . . . . ................................................ . . . . . . . . . .................................................. . .
... . . . . . . . . M. Li, C. Y. Lee, P. K. Venkatachala, A. ElShater, Y. Miyahara, K. Sobue, K. Tomioka, and U.-K. Moon 3555
A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive
Integrator ...................... . . . . . . . . . ................................. H. Zhang, Y. Zhu, R. P. Martins, and C.-H. Chan 3565
A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference
Decoupling Capacitor .................. . . . . . . . . . ................................... M. Zhan, L. Jie, Y. Zhong, and N. Sun 3576
A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact
Signal DAC .. . . . . . .......................................... H. Zhao, M. Zhang, Y. Zhu, R. P. Martins, and C.-H. Chan 3586
2023 INDEX ........... . . . . . . . . ................................................ . . . . . . . . . .... Available online at http://ieeexplore.ieee.org
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 58, NO. 12, DECEMBER 2023 3291
Guest Editorial
Introduction to the Special Section on
the 2023 IEEE International Solid-State
Circuits Conference (ISSCC)
T
HIS Special Section of IEEE JOURNAL OF SOLID-
STATE CIRCUITS (JSSC) highlights outstanding papers
presented at the 2023 IEEE International Solid-State Circuits
Conference (ISSCC), which was held from February 19 to
23, 2023, in San Francisco, USA, under the conference theme
“Building on 70 Years of Innovation in Solid-State Circuit
Design.” ISSCC is the foremost global forum for the presen-
tation of advances in solid-state circuits and systems-on-a-chip
and offers a unique opportunity for engineers working at the
cutting edge of integrated circuit (IC) design and application.
The conference includes several technical programs ranging
from analog to mixed-mode, digital, radio frequency (RF), and
power management circuits and systems with applications in
various fields. This JSSC Special Section highlights selected
papers from ISSCC, specifically on topics related to RF, wire-
less, analog, power management, and data converter circuits.
In 2023, ISSCC had a ∼30% acceptance rate, and more
than 2000 people attended the conference in person. This
Special Section of JSSC features 25 selected papers from
ISSCC 2023, of which, five papers are from the RF, five from
wireless, five from analog, six from power management, and
four from the data converters subcommittees. These papers
provide comprehensive materials extending their conference
proceedings and were carefully selected from highly qualified
accepted papers. The acceptance of these papers to JSSC was
based on a thorough peer review process. The accepted papers
cover a wide range of topics, as described below.
The papers selected out of the RF technical program
promote new advances ranging from digital power ampli-
fier techniques, low-power signal generation and frequency
synthesis, and tunable filtering approaches. The article by
Li et al. [A1] from Fudan University introduces a 28-nm
digital power amplifier that reaches an output power of
4.1 W through eight-way power combining. By manip-
ulating the in-phase and quadrature signal components
with transformer-based load modulation, the power ampli-
fier operates with an average efficiency exceeding 25.3%
at 6-dB output power backoff. This article illustrates an
extension of the state-of-the-art in linearity, efficiency, and
power for digital power amplifiers. The second article by
Shu and Luo [A2] from the University of Electronic Science
Digital Object Identifier 10.1109/JSSC.2023.3322181
and Technology of China introduces a scalable, multicore
oscillator that improves phase noise by utilizing a common-
mode resonance at twice the oscillation frequency to limit
the upconversion of flicker noise. The 28-GHz oscillator uses
20 cores to demonstrate a phase noise of −120.8 dBc/Hz
at 1-MHz offset. This work envisions massive scaling of
oscillator cores to achieve a desired phase noise target with low
power consumption. The third article by Dartizio et al. [A3]
of Politecnico di Milano describes advances in digital phase-
locked loops that linearize the response through the inverse
application of the digital-time-converter slope and subtrac-
tive dithering of the frequency control that randomizes the
quantization error of the delta-sigma modulator. The pro-
posed techniques reduce fractional spurs below −70 dBc with
low power consumption. The fourth article is prepared by
Choi et al. [A4] from the Korea Advanced Institute of Science
and Technology and introduces a cascaded frequency synthesis
approach that offers extremely low jitter while requiring a
single resonant tank to cover the 5G FR1 band. The first stage
is a low-noise phase-locked loop with a reduced frequency
tuning range that is multiplied through a second stage that
includes a ring-oscillator multiplier with a phase rotator.
The fractional spurs introduced through the multiplication
process in the ring oscillator cells are suppressed through
calibration to achieve an I/Q error of 0.16 degrees while the
rms jitter is under 135 fs. The final RF article authored by
Nagulu et al. [A5] from Washington University introduces a
tunable filter with a third-order filter response while producing
highly linear operation. Using a combination of intermediate
frequency and baseband filters, the high-order filter response
is constructed through a combination of dual series and shunt
equivalent resonators with an elliptical response that can push
operation to 5 GHz. A charge-pump clock booster circuit
enhances the power handling of the filter to 8.8 dBm while
offering an in-band third-order input intercept point of more
than 23 dBm.
In the area of wireless circuits, five papers are included.
The article by Agrawal et al. [A6] from Intel presents a
D-band receiver with an integrated analog-to-digital converter
(ADC) and a phase-locked loop (PLL). Implemented in 22-nm
FinFet COMS technology, the prototype achieves a peak
data rate of 128 Gb/s using 16-QAM modulation, consuming
1.95 pJ/b. The article by Fu et al. [A7] from the Tokyo
Institute of Technology introduces a low-power Ka-band
0018-9200 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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