IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 58, NO. 10, OCTOBER 2023 2671
Guest Editorial
Introduction to the Special Section on
the 2022 Asian Solid-State Circuits
Conference (A-SSCC)
T
HE Special Issue of the IEEE JOURNAL OF SOLID-
STATE CIRCUITS (JSSC) highlights outstanding papers
presented at the 2022 Asian Solid-State Circuits Conference
(A-SSCC), which was held from November 6 to 9, 2022 in
Taipei, Taiwan, under the conference theme “Silicon ICs
Enabling a Carbon Neutral World.” As one of the five con-
ferences fully supported by the IEEE Solid-State Circuits
Society, A-SSCC has gained prominence since its inception in
2005 as a leading global forum for showcasing advancements
in solid-state circuits and system-on-chip (SoC). In 2022,
A-SSCC adopted a hybrid format, allowing participants to
attend either in person or virtually via an online platform.
The conference had a record-high number of participants, with
594 attendees, where 345 attended physically and 249 joined
online.
In 2022, A-SSCC received 233 papers, out of which
89 were accepted, resulting in a 39% acceptance rate. This
Special Section of JSSC includes seventeen papers that provide
in-depth materials beyond what was published in the 2022
A-SSCC proceedings, carefully selected from the highly qual-
ified accepted papers. These papers cover a diverse range of
topics, from analog, power, biomedical, and RF circuits to
machine learning SoCs.
In analog and power circuits, three articles are included.
The first article [A1], presented by the Korea Advanced
Institute of Science and Technology (KAIST), Daejeon,
Republic of Korea, introduces a sleep timer that utilizes
an ultra-low-voltage frequency-locked-loop architecture with
a time-domain amplifier and a switch-less resistance mul-
tiplier. This design achieves a temperature dependency of
2.73 ppm/
◦
C while consuming only 63 nW at 0.4 V. The next
article from Peking University [A2] presents a cross-coupled,
current-mirror hybrid level shifter with a propagation delay of
20.08 ns and an energy consumption per transition of 18.11 fJ
for 0.3–1.2 V level conversion. The third article [A3], from
Korea University, focuses on an output capacitor-less NMOS
low-dropout regulator. This design incorporates wide-range
adaptive-gain nested Miller compensation and pre-emphasis
inverse biasing to ensure a small undershoot and overshoot
of 48 and 59 mV, respectively, against a large load current
change of 299 mA.
Digital Object Identifier 10.1109/JSSC.2023.3295522
In the area of data converters, the following articles intro-
duce state-of-the-art performances. Fudan University presents
an article [A4] that introduces a reference ripple mitigation
technique and an adaptively biased floating inverter ampli-
fier. These innovations enable the achievement of a 14-bit,
500 MS/s single-channel pipelined successive-approximation-
register (SAR) analog-to-digital converter (ADC). The Univer-
sity of Macau [A5] presents a time-interleaved noise-shaping
SAR ADC with a 30 MHz bandwidth and signal-to-noise
and distortion ratio (SNDR) of 73 dB. Finally, a fifth-order
multi-stage incremental delta sigma ADC for sensor interface
is presented by National Yang Ming Chiao Tung University
[A6], which achieves a figure-of-merit of 168.5 dB.
For biomedical and vision applications, four articles are
included. Sungkyunkwan University [A7] proposes an efficient
bit-level oversampling techniques for implantable intraocular
pressure monitoring systems. In the next article by Ajou Uni-
versity [A8], a 1984-pixel retinal prosthesis chip is introduced,
featuring time-domain in-pixel image processing and bipolar
stimulation. National Tsing Hua University [A9] presents
a multi-mode vision sensor chip that can extract temporal
and spatial information with in-sensor processing. Lastly,
KAIST [A10] presents an ultrasound transceiver IC with a
wide-bandwidth receiver and an on-chip transmitter for an
ultrasound capsule endoscopy system. It demonstrates success-
ful B-mode imaging in both the water tank and customized
phantom settings.
In the area of high-speed energy-efficient links, the article
from the National University of Singapore [A11] proposes
a new charge recycling logic that achieves over 20% power
reduction under random data streaming. The article [A12] from
the National Yang-Ming Jiao Tong University introduces a
10–26 Gbps energy-efficient receiver that incorporates dual
feedback nested-loop clock and data recovery circuit.
For artificial intelligence (AI), the following three articles
focus on improving the energy efficiency of machine learning
processors. First, KAIST [A13] presents an energy-efficient
spike domain deep-neural-network processor utilizing two-step
encoding and omni-sparsity handling unit to achieve state-of-
the-art energy efficiency of 13.7 TOPS/W for object detec-
tion and 31.5 TOPS/W for ImageNet classification. Next,
an energy-efficient Bayesian neural network accelerator is pro-
posed by Intel Labs [A14] with a highly efficient compute-in-
memory (CIM) macro and Gaussian random number generator.
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