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JANUARY 2022
VOLUME 57
NUMBER 1
IJSCBC
(ISSN 0018-9200)
SPECIAL SECTION ON THE 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS
CONFERENCE (ISSCC)
GUEST EDITORIAL
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC) ........
.................................................................. A. Amirkhany, T. Karnik, S. Das, J. Deguchi, and Y. Taito
3
SPECIAL SECTION PAPERS
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET ...........................
........................................................ J. Kim, S. Kundu, A. Balankutty, M. Beach, B. C. Kim, S. T. Kim,
Y. Liu, S. K. Murthy, P. Wali, K. Yu , H. S. Kim, C.-C. Liu, D. Shin, A. Cohen, Y. Segal, Y. Fan, P. Li, and F. O’Mahony
6
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS ...
.................................... Z. Wang, M. Choi, K. Lee, K. Park, Z. Liu, A. Biswas, J. Han, S. Du, and E. Alon
21
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7 -nm FinFET Wireline Receiver ...................
............... J. Bailey, H. Shakiba, E. Nir, G. Marderfeld, P. Krotnev, M.-A. LaCroix, D. Cassan, and D. Tonietto
32
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS ............
.............................................................. H. Li, C.-M. Hsu, J. Sharma, J. Jaussi, and G. Balamurugan
44
A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS ............................................. A. Atharav and B. Razavi 54
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative
Write With Verification and Online Read-Disturb Detection ................................................................
.................................. J.-H. Yoon, M. Chang, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, and A. Raychowdhury
68
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration .............................................
............................................................................... Q. Zhang, S. Su, C.-R. Ho, and M. S.-W. Chen
80
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain
Control .......................... C.-H. Huang, Y. Chen, X. Sun, A. Mandal, V. R. Pamula, N. Kurd, and V. S. Sathe
90
SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU ................................................................
...................................................... X. Liu, X. Li, H. Zhang, C. Li, L. Ren, Q. Chen, Y. Xu, and J. Yang
103
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed b y Task-Separated ASIL D
Control ............................................................................................... K. Matsubara, H. Lieske,
M. Kimura, A. Nakamura, M. Koike, S. Morikawa, Y. Hotta, T. Irita, S. Mochizuki, H. Hamasaki, and T. Kamei
115
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based
State-Retentive Sleep Mode ............................................................. D. Rossi, F. Conti, M. Eggimann,
A. Di Mauro, G. Tagliavini, S. Mach, M. Guermandi, A. Pullini, I. Loi, J. Chen, E. Flamand, and L. Benini
127
(Contents Continued on Back Cover)
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Digital Object Identifier 10.1109/JSSC.2021.3138285
JANUARY 2022
VOLUME 57
NUMBER 1
IJSCBC
(ISSN 0018-9200)
SPECIAL SECTION ON THE 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS
CONFERENCE (ISSCC)
GUEST EDITORIAL
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC) ........
.................................................................. A. Amirkhany, T. Karnik, S. Das, J. Deguchi, and Y. Taito
3
SPECIAL SECTION PAPERS
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET ...........................
........................................................ J. Kim, S. Kundu, A. Balankutty, M. Beach, B. C. Kim, S. T. Kim,
Y. Liu, S. K. Murthy, P. Wali, K. Yu, H. S. Kim, C.-C. Liu, D. Shin, A. Cohen, Y. Segal, Y. Fan, P. Li, and F. O’Mahony
6
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS ...
.................................... Z. Wang, M. Choi, K. Lee, K. Park, Z. Liu, A. Biswas, J. Han, S. Du, and E. Alon
21
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7 -nm FinFET Wireline Receiver ...................
............... J. Bailey, H. Shakiba, E. Nir, G. Marderfeld, P. Krotnev, M.-A. LaCroix, D. Cassan, and D. Tonietto
32
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS ............
.............................................................. H. Li, C.-M. Hsu, J. Sharma, J. Jaussi, and G. Balamurugan
44
A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS ............................................. A. Atharav and B. Razavi 54
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative
Write With Verification and Online Read-Disturb Detection ................................................................
.................................. J.-H. Yoon, M. Chang, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, and A. Raychowdhury
68
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration .............................................
............................................................................... Q. Zhang, S. Su, C.-R. Ho, and M. S.-W. Chen
80
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain
Control .......................... C.-H. Huang, Y. Chen, X. Sun, A. Mandal, V. R. Pamula, N. Kurd, and V. S. Sathe
90
SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU ................................................................
...................................................... X. Liu, X. Li, H. Zhang, C. Li, L. Ren, Q. Chen, Y. Xu, and J. Yang
103
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed b y Task-Separated ASIL D
Control ............................................................................................... K. Matsubara, H. Lieske,
M. Kimura, A. Nakamura, M. Koike, S. Morikawa, Y. Hotta, T. Irita, S. Mochizuki, H. Hamasaki, and T. Kamei
115
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based
State-Retentive Sleep Mode ............................................................. D. Rossi, F. Conti, M. Eggimann,
A. Di Mauro, G. Tagliavini, S. Mach, M. Guermandi, A. Pullini, I. Loi, J. Chen, E. Flamand, and L. Benini
127
140
153
167
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET ............... C. Schmidt, J. Wright, Z. Wang,
E. Chang, A. Ou, W. Bae, S. Huang, V. Milovanovi´c, A. Flynn, B. Richards, K. Asanovi ´c, E. Alon, and B. Nikoli´c
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security .........................................
....................................................................................... S. Taneja, V. K. Rajanna, and M. Alioto
Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation ..............
.................................................................. A. Ghosh, D. Das, J. Danial, V. De S. Ghosh, and S. Sen
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference,
and Workloa d-Aware Throttling ....................................... S. K. Lee, A. Agrawal, J. Silberman, M. Ziegler,
M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen, S. M. Mueller, J. Oh, M. Lutz, J. Jung,
S. Koswatta, C. Zhou, V. Zalani, M. Kar, J. Bonanno, R. Casatuta, C.-Y. Chen, J. Choi, H. Haynie, A. Herbert,
R. Jain, K.-H. Kim, Y. Li, Z. Ren, S. Rider, M. Schaal, K. Schelm, M. R. Scheuermann, X. Sun, H. Tran, N. Wang,
W. Wang, X. Zhang, V. Shah, B. Curran, V. Srinivasan, P.-F. Lu, S. Shukla, K. Gopalakrishnan, and L. Chang
182
Scalable and Programmable Neural Network Inference Accelerator Based o n In-Memory Computing ..................
.................................................. H. Jia, M. Ozatay, Y. Tang, H. Valavi, R. Pathak, J. Lee, and N. Verma
198
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for
Low-Noise Operation ..............................................................................................................
... J.-H. Kang, J. Yang, K. Kim, J.-H. Chae, G. Lee, S. Byeon, B. Kim, D.-H. Kim, Y. Kim, Y. Cho, J. Ji, S. Jeong,
J. Cha, M. Park, H. Kim, S. Park, S. Kim, H.-K. Jung, J. Jang, S. Lee, H. Kim, J.-H. Cho, J. Chun, and S. Cha
212
An 8 -Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling ................................
..................... T. M. Hollis, R. Schneider, M. Brox, T. Hein, W. Spirkl, M. Bach, M. Balakrishnan, S. Dietrich,
F. Funfrock, M. Ivanov, N. Jovanovic, M. Kuzmenka, D. Lauber, J. Ocon-Garrido, D. Ovard, K. P. Pfefferl,
S. Piatkowski, G. Piscopo, M. Plan, J. Polney, J. Pottgiesser, S. Rau, F. Vitale, M. Walter, M. Alvarez-Gonzalez,
C. Chetreanu, A. Sorrentino, J. Weller, P. Mayer, M. Richter, C. S . Garcia, A. Schneider, and S. N. Wong
224
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit ....
................................................ T. Song, H. Kim, W. Rim, H. Jung, C. Park, I. Lee, S. Baek, and J. Jung
236
REGULAR PAPERS
Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3 × Voltage Gain ..........
.................................................. V. K. Purushothaman, E. A. M. Klumperink, R. Plompen, and B. Nauta
245
Analysis and Design of High-Harmonic-Rejection Multi-Ratio mm-Wave Frequency Multipliers ........................
................................................................................................. J. Zhang, Y. Peng, and K. Kang
260
A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication ............................................
......................................................................................... S. Zhang, X. Zhou, C. Gao, and Q. Li
278
A Clock-Phase Reuse Technique for Discrete-Time Bandpass Filters .................. A. Bozorg and R. B. Staszewski 290
An On-Chip Power-Supply Noise Analyzer With Compressed Sensing and Enhanced Quantization ....................
....................................................................... P. Zhai, Z. Zhu, X. Zhou, Y. Cai, F. Zhang, and Q. Li
302
Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Ph otonics
Technology ............................ F. Bozorg i, M. Bruccoleri, E. Rahimi, M. Repossi, F. Svelto, and A. Mazzanti
312
A 51.3-TOPS/W, 134.4-GOPS In-Memory Binary Image Filtering in 65-nm CMOS ......................................
............................................................................................. S. K. Bose, D. Singla, and A. Basu
323
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 1, JANUARY 2022 3
Introduction to the Special Section on the 2021
IEEE International Solid-State
Circuits Conference (ISSCC)
I. INTRODUCTION
T
HIS Special Section of the IEEE JOURNAL OF SOLID-
S
TATE CIRCUITS is dedicated to a collection of the
best articles selected from the 2021 IEEE International
Solid-State Circuits Conference (ISSCC) that took place on
February 13–22, 2021, in San Francisco, CA, USA. This
Special Section covers articles from the Wireline, Digital
Circuits, Digital Architectures and Systems (DASs), Machine
Learning and AI, and Memory Committees.
II. W
IRELINE ARTICLES
Our wireline selection includes a mix of industry and
university papers on transmitters and receivers that push the
state of the art in speed and power efficiency. On the transmit
side, the trend of doubling the link data rates continued at
ISSCC 2021 by the introduction of the first 224-Gb/s PAM4
transmitter in 10-nm FinFET and a 200-Gb/s PAM4 transmitter
in 28 nm. This Special Section includes an extended version
of both papers with more details on implementation and
measurement data. The 224-Gb/s transmitter, designed by
Intel, incorporates a digital-to-analog converter, an 8-tap feed-
forward equalizer (FFE), and a quarter-rate output driver. The
200-Gb/s transmitter designed at the University of California
at Berkeley, on the other hand, deploys a segmented driver
architecture with reconfigurable FFE taps.
On the receive side, this section includes a complete
112-Gb/s PAM4 receiver, designed in a 7-nm FinFET by
Huawei, and a 100-Gb/s PAM4 optical receiver in 28-nm
CMOS by Intel. While the former implementation is an analog
to digital converter (ADC)/digital signal processing (DSP)-
based system, the latter design deploys sample-and-hold
circuits, analog FFE, and direct decision feedback equal-
izer (DFE) to achieve the desired performance. The 112-Gb/s
paper, in particular, pushes the state of the art in DFE design
for ADC-based systems by demonstrating a 9-tap sliding DFE.
Finally, this section includes a 56-Gb/s NRZ receiver in
a 28-nm process. The receiver, designed at the University
of California at Los Angeles, deploys a number of feed-
forward and feedback loops in the front-end to extend front-
end bandwidth and equalization capabilities, and achieve a
very good power efficiency in a relatively slow process.
III. D
IGITAL CIRCUITS ARTICLES
Four articles have been selected from digital circuits ses-
sions. The first article by Yoon et al. presents a 64-Kb
compute-in-memory (CIM) macro testchip fabricated in 40-nm
CMOS and RRAM process. It achieves a peak energy effi-
ciency of 56.67 TOPS/W while demonstrating the 8-bitline
Digital Object Identifier 10.1109/JSSC.2021.3127053
hybrid CIM/digital MAC operation with 1–8 b inputs and
weights, and 20 b outputs without quantization. The sec-
ond article by Zhang et al. presents a fractional-N digi-
tal multiplying delay-locked loop (MDLL) that employs a
digital-to-time converter to control the reference injection for
the fractional-N operation. The MDLL prototype fabricated
in 65-nm CMOS achieves −60 dBc fractional spur and
1.67-ps rms jitter at around 20-MHz offset. The third article
by Huang et al. presents a single inductor multiple output
(SIMO) converter with dynamic droop allocation and adaptive
clocking. These techniques implemented on an integrated
4-domain SIMO System on Chip (SoC) in 65-nm CMOS
show total system power reduction of 31%. The fourth article
by Liu et al. proposes a dynamic voltage-stacking scheme,
which supports two operating modes: a flat mode in the normal
state and a stack mode in the sleep state. The measurements
show that compared with the conventional flat architecture,
the dynamic voltage-stacking scheme reduces the sleep current
by 32.3% under the same circumstances, and it also improves
ULPMark-CP score by 23.6%, which is higher than the top1
in the ULPMark score list.
IV. D
IGITAL ARCHITECTURES AND SYSTEMS ARTICLES
In the DAS category, five articles from two sessions
have been selected. The first article by Matsubara et al.
presents a 12-nm autonomous driving SoC featuring a convo-
lutional neural network achieving 60.4 TOPS at 13.8 TOPS/W,
combined with task-separated Automotive Safety Integration
Level D (ASIL-D) control. The second article by Rossi et al.
showcases a wide-dynamic-range IoT SoC, achieving a com-
bination of 1.7 µW state-retentive sleep power and a peak-
performance of 32 GOPS at 1.3 TOPS/W efficiency. The third
article by Schmidt et al. presents an 8-core RISC-V-based SoC
designed entirely using an agile design methodology where
a generator-based design-flow enables a small-design team
to achieve silicon success with a complex 1.44 GHz, multi-
core 1.125 M-gate mixed-signal SoC. The fourth article by
Taneja et al. describes a novel unified true random number
generator (TRNG) and physically unclonable function (PUF)
architecture using a 16-Kb SRAM achieving 3.6-Mb/s TRNG
throughput and 1.78%–3.84% PUF BER in 28-nm CMOS. The
fifth article by Ghosh et al. describes an AES256 architecture
with a digital signal attenuation circuit and a time-varying
transfer function, improving security by 25% over existing
work.
V. M
ACHINE LEARNING ARTICLES
Two articles from the machine learning sessions of ISSCC
2021 have been selected. The first article by Lee et al.
presents a 7-nm 4-core AI chip that offers four types of mixed
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