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SEPTEMBER 2022 VOLUME 57

NUMBER 9

IJSCBC

(ISSN 0018-9200)

REGULAR PAPERS

Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s ................

...................................................................... P. Thomas, J. Finkbeiner, M. Grözing, and M. Berroth

2599

A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant

Wake-Up Receivers and Low-Noise Primary Receivers ......................................................................

.......... H. Bialek, A. Binaie, S. Ahasan, K. R. Sadagopan, M. L. Johnston, H. Krishnaswamy, and A. Natarajan

2611

A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL .............................

............................................................. K.-S. Choi, K.-M. Kim, D. R. Utomo, I.-Y. Lee, and S.-G. Lee

2626

A 0.4–6 GHz Receiver for Cellular and WiFi Applications ..................................... H. Razavi and B. Razavi 2640

A 164-μW 915-MHz Sub-Sampling Phase-Tracking Zero-IF Receiver With 5-Mb/s Data Rate for Short-Range

Applications ........................................................................................................................

... Y. Guo, Z. Fang, K. Tang, Z. Weng, C. Yang, N. Wang, E. J. Ng, Z. Wang, C.-H. Heng, H. Jiang, and Y. Zheng

2658

A Current Re-Use Quadrature RF Receiver Front-End for Low Power Applications: Blixator Circuit ..................

........................................................................ M. Barzgari, A. Ghafari, M. Meghdadi, and A. Medi

2672

W-band Scalable 2 × 2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate

Communication ............................... H. Li, J. Chen, D. Hou, Z. Li, R. Zhou, Z. Chen, P. Yan, and W. Hong

2685

A 24–29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM

and 400-MHz 256-QAM for 5G New Radio ......... Y. Yi, D. Zhao, J. Zhang, P. Gu, Y. Chai, H. Liu, and X. You

2702

A Reconﬁgurable DC-DC Converter for Maximum Thermoelectric Energy Harvesting in a Battery-Powered

Duty-Cycling Wireless Sensor Node .................................... Y.-S. Noh, J.-I. Seo, H.-S. Kim, and S.-G. Lee

2719

A 94.3% Peak Efﬁciency Adaptive Switchable CCM and DCM Single-Inductor Multiple-Output Converter With 0.03

mV/mA Low Crosstalk and 185 nA Ultralow Quiescent ....................................................................

...... T.-H. Yang, Y.-H. Wen, Y.-J. Ouyang, C.-K. Chiu, B.-K. Wu, K.-H. Chen, Y.-H. Lin, S.-R. Lin, and T.-Y. Tsai

2731

A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing ......................................................

.......................... P. Garcha, V. Schaffer, B. Haroun, S. Ramaswamy, J. Wieser, J. Lang, and A. Chandraksan

2741

A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm

CMOS ......................................................................................................... A. Uran, K. Ture,

C. Aprile, A. Trouillet, F. Fallegger, E. C. M. Revol, A. Emami, S. P. Lacour, C. Dehollain, Y. Leblebici, and V. Cevher

2752

(Contents Continued on Back Cover)

IEEE JOURNAL OF SOLID-STATE CIRCUITS

The IEEE JOURNAL OF SOLID-STATE CIRCUITS is published by the IEEE Solid-State Circuits Society. For membership and subscription information and pricing, please visit

www.ieee.org/membership-catalog.

SOLID-STATE CIRCUITS SOCIETY

http://sscs.org

President

J. L

ONG

University of Waterloo

Waterloo, ON, Canada

Vice President

B. B

OWHILL

Intel

Framingham MA

Secretary

E. A

YRANCI

Peregrine Semiconductor

San Diego, CA, USA

Treasurer

T. S. F

IEZ

Univ. of Colorado Boulder

Boulder, CO, USA

Past-President

K. K. O

Univ. Texas at Dallas

Richardson, TX, USA

Executive Ofﬁce

[email protected]

Executive Director:

A. G

REENBERG

phone: 732 465-6459

a.greenberg@ieee.org

ADMINISTRATIVE COMMITTEE

Elected for 2020-2022 Term

A. C

ATHELIN

STMicroelectronics

Crolles, France

Elected for 2021-2023 Term

I. F

UJIMORI

Broadcom Corporation

Irvine, CA, USA

Elected for 2023-2024 Term

D. G

RIFFITH

Texas Instruments

USA

V. K. D

Intel Corp

Hillsboro, OR, USA

R. M

ULLER

University of California, Berkeley

Berkeley, CA, USA

C. K

Korea University

Seoul, Republic of Korea

M. I

KEDA

University of Tokyo

Tokyo, Japan

K. N

ISHIMURA

Panasonic

Moriguchi, Japan

F. O’M

AHONY

Intel

Hillsboro, OR

A. L. L

OKE

Qualcomm

San Diego, CA, USA

E. R

ODRIGUEZ-VILLEGAS

Imperial College London

London, England, United Kingdom

F. S

HEIKH

Intel

Portland, OR

M. N

AGATA

Kobe University

Kobe Hyogo, Japan

H. Y

Korea Advanced Institute of

Science and Technology

Daejeon, South Korea

Y. O

IKE

Sony

Kanagawa, Japan

W. R

HEE

Institute Of Microelectronics

Tsinghua University

Beijing, China

STANDING COMMITTEE CHAIRS

Awards

J. J. C

ORCORAN

Keysight Technologies

Retired

Chapters

A. L. L

OKE

Qualcomm

San Diego, CA, USA

Education/Distinguished

Lecturer Program

A. S

HEIKHOLESLAMI

University of Toronto

Toronto, ON, Canada

Meetings

A. P

IOVACCARI

Austin, TX, USA

Membership

D. F

RIEDMAN

IBM

Yorktown Heights,

NY, USA

Nominations

K. K. O.

Univ. Texas at Dallas

Richardson, TX, USA

Publications

S. P

AVA N

Indian Institute of

Technology, Madras

Chennai, India

Women in Circuits

K. W

ILCOX

AMD

Boxborough, MA, USA

EDITOR

AVA N KUMAR HANUMOLU,EDITOR-IN-CHIEF

University of Illinois, Urbana-Champaign

413 CSL, 1308 W. Main St, Urbana, IL, USA

[email protected]

Associate Editors

P. A NDREANI

Dept. of Electr. Inf. Technol.

Lund Univ.

221 00 Lund, Sweden

[email protected]

M.-F. (M

ARVIN)CHANG

Department of Electrical

Engineering

National Tsing Hua

University (NTHU)

Hsinchu, Taiwan

[email protected]

V. D

Intel Corp.

Hillsboro, OR 97124, USA

vivek.[email protected]

Y. D

ONG

Analog Devices, Inc.

Newton, MA, 02466, USA

[email protected]

D. F

RIEDMAN

Thomas J. Watson Research Center

Yorktown Heights, NY 10598, USA

[email protected]

D. G

RIFFITH

Texas Instruments

Dallas, TX 75243, USA

danielle.grifﬁ[email protected]

P. H

EYDARI

UC Irvine

Irvine, CA 92697, USA

[email protected]

W. H. K

Dept. Electronic Comp. Eng.

HKUST

Hong Kong, China

[email protected]

J. K

Seoul National University

Seoul, Republic of Korea

[email protected]

P.-I. M

State Key Lab of

Analog & Mixed-Signal VLSI

Univ. of Macau

Macau, China

[email protected]

P. M

ALCOVATI

Univ. of Pavia

27100 Pavia, Italy

piero.malcovati@unipv.it

A. N

ATARAJAN

School of Electrical Engineering

and Computer Science,

Oregon State University

Corvallis, OR 97331-5501, USA

[email protected]

K. O

KADA

Dept. Phys. Electron.

Graduate Sch. Sci. Eng.

Tokyo Inst. of Technology

Tokyo 152-8552, Japan

[email protected].jp

H. P

Broadcom Limited

Irvine, CA 92618 USA

[email protected]

S. P

AVA N

Dept. Electr. Eng.

Indian Institute of Technology,

Madras

Chennai, India 600 036

[email protected]

P. R

EYNAERT

KU Leuven ESAT-MICAS

Leuven, B3001, Belgium

patrick.reynaert@kuleuven.be

D. S

TOPPA

Heptagon-AMS group

Moosstrasse 2

CH-8803 R¨uschlikon, Switzerland

[email protected]

D. S

YLVESTER

Dept. Electr. Eng. Comput. Sci.

Univ. Michigan

Ann Arbor, MI 48109-2122

[email protected]

N. V

AN HELLEPUTTE

Systems & Circuits for

Connected Health

IMECbe

Leuven I Belgium

Nick.V[email protected]

IEEE Ofﬁcers

K. J. RAY LIU, President & CEO

AIFUR RAHMAN, President-Elect

OHN W. WALZ, Director & Secretary

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AWR ENCE O. HALL, Director & Vice President, Publication Services and Products

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AMES E. MATTHEWS, Director & President, Standards Association

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Senior Manager, Journals Production: KATIE SULLIVAN Journals Production Manager: SARA T. SCUDDER

IEEE JOURNAL OF SOLID-STATE CIRCUITS (ISSN 0018-9200) is published monthly by The Institute of Electrical and Electronics Engineers, Inc. Responsibility for the contents rests upon the

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Digital Object Identiﬁer 10.1109/JSSC.2022.3195583

SEPTEMBER 2022 VOLUME 57

NUMBER 9

IJSCBC

(ISSN 0018-9200)

REGULAR PAPERS

Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s ................

...................................................................... P. Thomas, J. Finkbeiner, M. Grözing, and M. Berroth

2599

A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant

Wake-Up Receivers and Low-Noise Primary Receivers ......................................................................

.......... H. Bialek, A. Binaie, S. Ahasan, K. R. Sadagopan, M. L. Johnston, H. Krishnaswamy, and A. Natarajan

2611

A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL .............................

............................................................. K.-S. Choi, K.-M. Kim, D. R. Utomo, I.-Y. Lee, and S.-G. Lee

2626

A 0.4–6 GHz Receiver for Cellular and WiFi Applications ..................................... H. Razavi and B. Razavi 2640

A 164-μW 915-MHz Sub-Sampling Phase-Tracking Zero-IF Receiver With 5-Mb/s Data Rate for Short-Range

Applications ........................................................................................................................

... Y. Guo, Z. Fang, K. Tang, Z. Weng, C. Yang, N. Wang, E. J. Ng, Z. Wang, C.-H. Heng, H. Jiang, and Y. Zheng

2658

A Current Re-Use Quadrature RF Receiver Front-End for Low Power Applications: Blixator Circuit ..................

........................................................................ M. Barzgari, A. Ghafari, M. Meghdadi, and A. Medi

2672

W-band Scalable 2 × 2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate

Communication ............................... H. Li, J. Chen, D. Hou, Z. Li, R. Zhou, Z. Chen, P. Yan, and W. Hong

2685

A 24–29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM

and 400-MHz 256-QAM for 5G New Radio ......... Y. Yi, D. Zhao, J. Zhang, P. Gu, Y. Chai, H. Liu, and X. You

2702

A Reconﬁgurable DC-DC Converter for Maximum Thermoelectric Energy Harvesting in a Battery-Powered

Duty-Cycling Wireless Sensor Node .................................... Y.-S. Noh, J.-I. Seo, H.-S. Kim, and S.-G. Lee

2719

A 94.3% Peak Efﬁciency Adaptive Switchable CCM and DCM Single-Inductor Multiple-Output Converter With 0.03

mV/mA Low Crosstalk and 185 nA Ultralow Quiescent ....................................................................

...... T.-H. Yang, Y.-H. Wen, Y.-J. Ouyang, C.-K. Chiu, B.-K. Wu, K.-H. Chen, Y.-H. Lin, S.-R. Lin, and T.-Y. Tsai

2731

A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing ......................................................

.......................... P. Garcha, V. Schaffer, B. Haroun, S. Ramaswamy, J. Wieser, J. Lang, and A. Chandraksan

2741

A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm

CMOS ......................................................................................................... A. Uran, K. Ture,

C. Aprile, A. Trouillet, F. Fallegger, E. C. M. Revol, A. Emami, S. P. Lacour, C. Dehollain, Y. Leblebici, and V. Cevher

2752

A 96.9-dB-Resolution 109-μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed

Single-Ended Resistance Readout in 180-nm CMOS ......................... E. Sacco, J. Vergauwen, and G. Gielen

2764

An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter ..................................

...................................................................... C. Lim, Y. Choi, J. Song, S. Ahn, S. Jang, and C. Kim

2778

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique ........ D.-R. Oh, M.-J. Seo, and S.-T. Ryu 2791

A 12-GHz Reconﬁgurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconﬁguration

Switches on Phase Noise ........................... L. Tomasin, P. Andreani, G. Boi, F. Padovan, and A. Bevilacqua

2802

Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using

8th-Order Transformer-Based Resonator in 40 nm CMOS ........................................ Q. Jiang and Q. Pan

2812

An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based

Phase Detector .............................................................. S. Park, S. Choi, S. Yoo, Y. Cho, and J. Choi

2829

A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s

Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping M .............................

........................................................................... C. Hwang, H. Park, Y. Lee, T. Seong, and J. Choi

2841

A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance ................................ G. Hou and B. Razavi 2856

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and

Temperature-Independent ADC References ............................. W. Li, X. Sun, S. Huang, H. Jiang, and S. Yu

2868

Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing ...............................

.......................................... A. Jain, A. M. Veggetti, D. Crippa, A. Benfante, S. Gerardin, and M. Bagatin

2878

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 9, SEPTEMBER 2022 2599

Time-Interleaved Switched Emitter Followers to

Extend Front-End Sampling Rates to up to 200 GS/s

Philipp Thomas , Member, IEEE, Jakob Finkbeiner , Graduate Student Member, IEEE,

Markus Grözing , Member, IEEE, and Manfred Berroth , Senior Member, IEEE

Abstract—Optical transceivers with more than 50 GBd are

now being deployed, while the use of more than 100 GBd

is currently under investigation. CMOS components, such as

the analog-to-digital converter (ADC) in the receiver path,

can be highly parallelized for higher sampling rates but are

difﬁcult to scale toward higher analog bandwidths. Thus, the

hybrid integration of front-end circuits with the function of a

bandwidth gearbox in other semiconductor technologies is an

interesting research topic. In this article, we show an example

of a time-interleaved analog demultiplexer (ADeMUX) with

four track-and-hold (T/H) circuits based on switched emitter

followers (SEFs) in a 90-nm silicon-germanium (SiGe)-Bipolar

CMOS (BiCMOS) technology for parallel operation of four

CMOS ADCs. The 50% duty cycle of the clock signal facilitates

its generation and can save power consumption in the clock

path or enable higher sampling rates compared with the 25%

duty-cycle clock of other ADeMUX architectures. We show that

using switched preampliﬁers in front of the SEFs can double the

bandwidth of each T/H lane. Experimental veriﬁcation shows up

to 57-GHz input bandwidth while requiring only 16-GHz input

bandwidth for each of the ADCs that can be connected to the four

32-GS/s output channels. The circuit achieves 3–6-bit accuracy

and is suitable for 100-GBd signaling and beyond with pulse

amplitude modulation. To demonstrate the capability of higher

sampling rates, measurement results at 4 × 50 GS/s = 200 GS/s

are provided as well although signiﬁcant advancement of the

measurement environment is needed for a complete evaluation.

Index Terms—Analog-to-digital conversion, bipolar

CMOS (BiCMOS) integrated circuits, demultiplexing, sampled

data circuits, silicon germanium.

I. INTRODUCTION

IME interleaving has become a vital part of ultra-high-

speed transceivers in wireline and optical communication

Manuscript received 7 March 2022; revised 11 June 2022; accepted

12 July 2022. Date of current version 26 August 2022. This article was

approved by Guest Editor Yuriy Greshishchev. This work was supported in

part by the European Union within the ECSEL-JU H2020 project Towards

Advanced BiCMOS Nanotechnology Platforms for RF and THz Applications

(TARANTO) under Grant 737454, in part by the German Federal Ministry

of Education and Research under Grant 16ESE0210, and in part by the

German Research Foundation within the Priority Program SPP 2111 under

Grant BE2256/34-1. (Corresponding author: Philipp Thomas.)

Philipp Thomas was with the Institute of Electrical and Optical Communi-

cations Engineering, University of Stuttgart, 70569 Stuttgart, Germany. He is

now with the Nokia Bell Labs, New Providence, NJ 07974 USA (e-mail:

philipp.thomas@nokia-bell-labs.com).

Jakob Finkbeiner, Markus Grözing, and Manfred Berroth are with the

Institute of Electrical and Optical Communications Engineering, University

of Stuttgart, 70569 Stuttgart, Germany.

Color versions of one or more ﬁgures in this article are available at

https://doi.org/10.1109/JSSC.2022.3192546.

Digital Object Identiﬁer 10.1109/JSSC.2022.3192546

Fig. 1. Application of a SiGe voltage-mode ADeMUX using a 50% duty-

cycle clock with an external CMOS ADC-DSP. SPA: switched preampliﬁer.

SEF: switched emitter follower.

links. CMOS technology is well known for its high integration

density, which facilitates parallel signal processing to allow

ultra-high symbol rates of 50 GBd and beyond that are

required in state-of-the-art applications.

However, the front-end building blocks, such as analog mul-

tiplexers (AMUX) in the transmitter and analog demultiplexers

(ADeMUX) in the receiver often, are the bottleneck for higher

bandwidths. Thus, the design of such analog front ends in

silicon-germanium (SiGe)-Bipolar CMOS (BiCMOS) and InP

technologies has gained traction in recent years to enable

wireline and optical transceivers with 100 GBd and beyond.

The required ultra-broadband sampling circuits for the ADe-

MUX fall into the categories of either charge-sampling cur-

rent integrators or switched emitter followers (SEFs). Recent

advances with charge-sampling track-and-hold (T/H) and

ADeMUX circuits have shown their potential to receive data at

100–128 GBd [1]–[4]. Their architecture is largely insensitive

to clock jitter, but very short clock pulses of only a few

picoseconds are required since the acquisition time dictates

their bandwidth. SEF-based T/H circuits have an inherently

short acquisition time and can extend the bandwidth of a sam-

pling front end even further to up to 110 GHz [5]–[14]. Sam-

pling operation is documented at up to 108 GS/s for single-

core T/H circuits and up to 200 GS/s for time-interleaved

architectures in SiGe-BiCMOS technologies [6], [7]. Analog-

to-digital converters (ADCs) with integrated T/H functionality

See https://www.ieee.org/publications/rights/index.html for more information.

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