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The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. 《JSSC_202104》是IEEE固态电路期刊中的一期特刊，专注于固态电路领域的深入研究，特别是集成电路的晶体管级设计。这期期刊聚焦于2020年VLSI电路研讨会的专题论文，涵盖了一系列与微电子技术相关的创新成果。其中一篇论文介绍了直接TOF扫描LiDAR传感器，它采用了两步多事件直方图TDC（时间数字转换器）和嵌入式干扰滤波器。这项技术提升了光探测和测距系统的精度和性能，对于自动驾驶、机器人导航等领域有着重要意义。另一篇论文提出了一个200微瓦的高分辨率涡流位移传感器接口。该设计低功耗、高效能，可应用于精密测量和工业自动化系统，提高了对微小位移变化的检测能力。还有一篇关于VCO（压控振荡器）为基础的传感器前端的研究，通过背景校准的差分脉冲编码调制实现了112dB的SFDR（信噪比失真点）和89dB的SNDR（信噪比）。这种技术改进了传感器前端的性能，增强了信号处理能力，适用于无线通信和雷达系统。针对环境监测和健康护理，有一篇论文展示了一个0.6V、785纳瓦的多模传感器接口IC，用于臭氧污染物感应和心血管疾病监测。这一低功耗解决方案有助于实时环境监控和个人健康管理。此外，还有一篇论文介绍了一种超低功耗图像信号处理器，用于层次化图像识别的深度神经网络。该处理器优化了能源效率，提高了图像处理速度，适用于物联网设备和智能相机应用。一篇论文提出了一个617-TOPS/W（每瓦运算次数）的全数字二进制神经网络加速器，采用10纳米FinFET CMOS工艺。这种架构利用了稀疏性，实现了能量效率更高的深度神经网络计算，为人工智能应用提供了强大的硬件支持。这些论文展示了固态电路领域的最新进展，包括传感器技术、低功耗设计、信号处理和神经网络加速器，这些都反映了当前微电子学界在提升性能、降低能耗以及优化计算效率方面的不懈追求。

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APRIL 2021

VOLUME 56

NUMBER 4

IJSCBC

(ISSN 0018-9200)

SPECIAL ISSUE ON THE 2020 SYMPOSIUM ON VLSI CIRCUITS

GUEST EDITORIAL

Introduction to the Special Issue on the 2020 Symposium on VLSI Circuits ....... ....... ... B. Ginsburg and Y. Oike 1019

SPECIAL ISSUE PAPERS

Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embe dded Interferenc e

Filter ..................................... ....... . H. Seo, H. Yoon, D. Kim, J. Kim, S.-J. Kim, J.-H. Chun, and J. Choi

1022

A 200-μW Interface for High-Resolution Eddy-Current Displacement Sensors ...... ....... ......... ....... ................

.................................. M. Pimenta, Ç. Gürleyük, P. Walsh, D. O’Keeffe, M. Babaie, and K. A. A. Makinwa

1036

A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse

Code Modulation .. .. .. .......................................................................... J. Huang and P. P. Mercier

1046

A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease

Monitoring ................................. R. Agarwala, P. Wang, H. L. Bishop, A. Dissanayake, and B. H. Calhoun

1058

An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural

Networks ......................................................... H. An, S. Schiferl, S. Venkatesan, T. Wesley, Q. Zhang,

J. Wang, K. D. Choo, S. Liu, B. Liu, Z. Li, L. Gong, H. Zhong, D. Blaauw, R. Dreslinski, H. S. Kim, and D. Sylvester

1071

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS ......... ....... ....... ...... ..

.......................................................................................................... P. C. Knag, G. K. Chen,

H. E. Sumbul, R. Kumar, S. K. Hsu, A. Agarwal, M. Kar, S. Kim, M. A. Anders, H. Kaul, and R. K. Krishnamurthy

1082

Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for

Energy-Efﬁcient Deep Neural Networks ............................. J.-H.Kim,J.Lee,J.Lee,J.Heo,andJ.-Y.Kim

1093

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator .. ..... .......

............................................................................................................. Z.Li,Z.Wang,L.Xu,

Q. Dong, B. Liu, C.-I. Su, W.-T. Chu, G. Tsou, Y.-D. Chih, T.-Y. J. Chang, D. Sylvester, H.-S. Kim, and D. Blaauw

1105

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free

Condition ... .... ... ...... .............. ....... ....... ....... .... ....... .............. .... ......... ....... ....... ....... M. Natsui,

A. Tamakoshi, H. Honjo, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka,

Y. Noguchi, M. Yasuhira, Y. Ma, H. Shen, S. Fukami, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu

1116

A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and

High-Capacity Storage ............................................................................................................

... D. Na, J.-w. Lee, S.-K. Lee, H. Cho, J. Lee, M. Yang, E. Song, A. Kavala, T. Kim, D.-S. Jang, Y. Jo, J.-Y. Shin,

B.-K. Chun, T.-s. Lee, B. Jeong, C.-W. Yoon, D. Kang, S. Lee, J. Ihm, D. S. Byeon, J. Lee, and J. H. Song

1129

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm

CMOS ............................................................................................ R. Kumar, X. Liu, V. Suresh,

H. K. Krishnamurthy, S. Satpathy, M. A. Anders, H. Kaul, K. Ravichandran, V. De, and S. K. Mathew

1141

MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor

Josephson Junction Dev ices .......... C. L. Ayala, T. Tanaka, R. Saito, M. Nozoe, N. Takeuchi, and N. Yoshikawa

1152

A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon

Processor .......................................

......................................................... V. K. Kalyanam, E. Mahurin, K. A. Bowman, and J. A. Abraham

1166

A High-Linearity and Low-EMI Multilevel Class-D Ampliﬁer .......... ..... ........... ..... ........... ..... ............. ....

................... H. Zhang, S. Karmakar, L. J. Breems, Q. Sandifort, M. Berkhout, K. A. A. Makinwa, and Q. Fan

1176

An Automo tive-Use Battery-to-Load GaN-Based Switching Power Converter With Anti-Aliasing MR-SSM and

In-Cycle Adaptive ZVS Techniques .................................................................. D. Yan and D. B. Ma

1186

A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for

Battery-Monitoring Applications .................................................................................................

..................................... J.-H. Boo, K.-I. Cho, H.-J. Kim, J.-G. Lim, Y.-S. Kwak, S.-H. Lee, and G.-C. Ahn

1197

A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW ............................ .

............................................ E. Eland, S. Karmakar, B. Gönen, R. van Veldhoven, and K. A. A. Makinwa

1207

An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Ampliﬁers in 28-nm

CMOS ........................................... D.-R. Oh, K.-J. Moon, W.-M. Lim, Y.-D. Kim, E.-J. An, and S.-T. Ryu

1216

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic

Scope-on-Chip Background Monitoring in 16 nm ............................................................................

........................................ B. Hershberg, N. Markuli´c, J. Lagos, E. Martens, D. Dermit, and J. Craninckx

1227

A 0.5-V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator With 96.1-ppm/

◦

C Steady-State Stability Using a Duty-Cycled

Digital Frequency-Locked Loop .............................................. D. S. Truesdell, S. Li, and B. H. Calhoun

1241

A Power-Efﬁcient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain ........ .....

................................................................................... L. Wu, T. Burger, P. Schönle, and Q. Huang

1254

ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET ....... ...... ..... ....... ........... ....... .....

.............. H. Lin, C. Boecker, M. Hossain, S. Tangirala, R. Vu, S. D. Vamvakos, E. Groen, S. Li, P. Choudhary,

N. Wang, M. Shibata, H. Taghavi, M. van Ierssel, A. Maniyar, A. Wodkowski, K. Brar, N. Nguyen, and S. Desai

1265

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impe dance-Matched Driver and

Three-Point ZQ Calibration for Memory Interface ............................................................................

..................................................... Y.-U. Jeong, H. Park, C. Hyun, J.-H. Chae, S.-H. Jeong, and S. Kim

1278

A Dual-Mode Wi-Fi/BLE Wake-Up Receiver ........ ..... ...... ..... ..... ...... ..... ..... P.-H. P. Wang and P. P. Mercier 1288

A 0.6-mW 16-FSK Receiver Achieving a Sensitivity of −103 dBm at 100 kb/s ...........................................

........................................................................... A. Nikoofard, H. Abbasi Zadeh, and P. P. Mercier

1299

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation f or 5G MIMO

Systems ....................................................................................... J. Pang, Z. Li, X. Luo, J. Alvin,

R. Saengchan, A. A. Fadila, K. Yanagisawa, Y. Zhang, Z. Chen, Z. Huang, X. Gu, R. Wu, Y. Wang, D. You, B. Liu,

Z. Sun, Y. Zhang, H. Huang, N. Oshima, K. Motoi, S. Hori, K. Kunihiro, T. Kaneko, A. Shirane, and K. Okada

1310

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 56, NO. 4, APRIL 2021 1019

Introduction to the Special Issue on the

2020 Symposium on VLSI Circuits

HIS Special Issue of the IEEE JOURNAL OF SOLID-

TATE CIRCUITS highlights some of the best papers

presented at the Symposium on VLSI Circuits, held on

June 15–19, 2020. Due to the Covid-19 pandemic, this was

the ﬁrst VLSI Symposium that was held fully virtual. While it

is difﬁcult to replace all of the interactions of an in-person con-

ference, the symposium featured all of the technical material,

including regular and invited papers, plenaries, short courses,

and a forum. In addition, new content was added, including

a series of executive sessions where paper authors, technical

program committee members, and the audience engaged in

open discussions on key topics related to our ﬁeld. While the

live events were concentrated in that one week, on demand

content was available through the end of August for partici-

pants to view at their leisure.

Founded in 1987, the Symposium on VLSI Circuits is

jointly sponsored by the IEEE Solid-State Circuits Society

and the Japan Society of Applied Physics in cooperation

with the Institute of Electronics, Information, and Commu-

nications Engineers and the IEEE Electron Devices Society.

The Symposium on VLSI Circuits is jointly organized and

colocated with the Symposium on VLSI Technology and

thus provides excellent opportunities for interactions among

integrated circuit and technology experts on topics of mutual

interest. As the new normal emerges, the VLSI Symposia are

committed to developing new ways to deliver content and to

providing enhanced opportunities for interaction.

The 2020 Symposium on VLSI Circuits received 321 sub-

missions. The program committees selected 110 papers for

presentation with subjects including digital circuits, proces-

sors, SoCs, machine learning accelerators, memories, biomed-

ical circuits, sensors and displays, power conversion circuits,

analog ampliﬁers and ﬁlters, wireless and wireline commu-

nications, data converters, frequency generation, and clock

circuits. This issue of the journal includes 26 outstanding

articles selected as highlights of the work presented at the

2020 Symposium. The journal articles describe the work

introduced at the symposium with greater detail than pro-

vided by corresponding papers in the symposium digest. The

articles were subject to the standard journal review process.

We enjoyed working with the authors on these articles, and

we certainly hope that the technical details presented in these

articles will be interesting and useful to journal readers. The

following paragraphs give an overview regarding the article

content of this Special Issue.

The ﬁrst article presents a robust light detection and rang-

ing (LiDAR) system with an embedded interference ﬁlter.

Digital Object Identiﬁer 10.1109/JSSC.2021.3059008

Researchers from Sungkyunkwan University, SOS LAB, and

Samsung Electronics demonstrate a reliable 36-channel direct

time-of-ﬂight measurement even when 32 different LiDARs

interfere.

The next three articles advance sensor front-ends. For

safety-critical touch applications, the Delft University of Tech-

nology and Cypress Semiconductor achieve a low-power eddy-

current sensor interface with a power consumption of 200 μW

from 1.8-V power supply. Authors from the University of

California at San Diego (UCSD) achieve a 112-dB spurious

free dynamic range (SFDR) and 89-dB signal-to-noise and dis-

tortion ratio (SNDR) voltage control oscillator (VCO)-based

sensor front-end. The University of Virginia presents a 785-nW

multimodal sensor interface IC for ozone pollutant sensing

and correlated cardiovascular disease monitoring based on

electrocardiography (ECG) and photoplethysmography (PPG).

With the advancement of deep neural networks (DNNs),

a more efﬁcient processing architecture is desired. A DNN-

based image signal processor presented by the Univer-

sity of Michigan achieves hierarchical image recognition

with 170 μW at 5 f/s. Authors from Intel demonstrate a

617 TOPS/W digital binary neural network accelerator in

10-nm FinFET CMOS. An energy-efﬁcient processing-in-

memory (PIM) architecture proposed by the Korea Advanced

Institute of Science and Technology achieves more than

2.1 times improvement over the state-of-the-art PIM imple-

mentations. Researchers from the University of Michigan

and Taiwan Semiconductor Manufacturing Company (TSMC)

also demonstrate an energy-efﬁcient DNN accelerator fea-

turing 24-Mbit random access memory (RAM) as all-on-

chip weight storage to eliminate energy-consuming off-chip

memory accesses.

The next two articles showcase the state-of-the-art memory

implementations. A dual-port spin-orbit-torque magnetore-

sistive random access memory (SOT-MRAM) presented by

Tohoku University and JST ACCEL achieves 90-MHz read

and 60-MHz write operations under ﬁeld-assistance-free con-

ditions. Samsung Electronics shows a 1.2 V, 1.8 Gb/s/pin, and

16-Tb

NAND ﬂash memory multi-chip package incorporating

16 dies of 1-Tb

NAND ﬂash memory each.

To address the demands of increasing security, Intel demon-

strates a side-channel attack (SCA) hardened AES-128 and

RSA cryptoprocessor in 14-nm CMOS using a nonlinear dig-

ital low-dropout regulator with control loop randomizations.

Two microprocessor articles advance the processor

architecture to improve energy efﬁciency. Yokohama National

University demonstrates the ﬁrst successful adiabatic

microprocessor using 1.4-zJ/op Josephson junction devices

manufactured using an Nb/AlOx/Nb superconductor process.

Researchers from Qualcomm Technologies and The University

See https://www.ieee.org/publications/rights/index.html for more information.

1020 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 56, NO. 4, APRIL 2021

of Texas at Austin present a proactive clock-gating system in

a 7-nm digital signal processor (DSP) to enable a 5% supply

voltage reduction.

The next two articles demonstrate advances in automotive

electronics, which have demanding electromagnetic interfer-

ence (EMI) requirements. Researchers from the Delft Uni-

versity of Technology, NXP Semiconductors, and Goodix

Technologies demonstrate a class-D audio ampliﬁer that meets

the CISPR 25 Class 5 EMI standard and achieves a minimum

total harmonic distortion plus noise (THD+N) of −107.8 dB.

Using multirate spread-spectrum modulation, authors from the

University of Texas at Dallas reduce the peak EMI by 29% in

a GaN-based power converter.

For battery monitoring applications, it is necessary to

achieve high precision over a wide operating temperature

range. Using only a single trim, Sogang University presents

a switched capacitor CMOS bandgap with 3σ inaccuracy of

<0.12% from −40

◦

C to 125

◦

The next three articles advance the state of the art in analog-

to-digital converters (ADCs). A discrete-time zoom ADC for

audio applications is described by the Delft University of

Technology and NXP Semiconductors. Combining a 5-bit

successive approximation register (SAR) ADC and a third-

order sigma–delta modulator, it achieves 109.8-dB dynamic

range over 20-kHz bandwidth. At the opposite end of operating

bandwidth, the Korea Advanced Institute of Science and Tech-

nology combines a loop-unrolled SAR ADC and an interpolat-

ing ﬂash to achieve more than 45 dB of SNDR with a 3-GHz

effective resolution bandwidth (ERBW). Finally, to address

applications with widely varying speed requirements, imec

presents a ringamp-based pipelined ADC in 16-nm CMOS

that can maintain a Walden-FoM of 14 fJ/conversion-step from

1MS/sto1GS/s.

Two clocking articles showcase performance that spans

many orders of magnitude of operating frequency. The Uni-

versity of Virginia presents a 560-kHz oscillator that uses

a duty-cycled digital frequency-locked loop that periodically

stabilizes its output frequency. At steady-state conditions,

the oscillator reaches 96.1 ppm/

◦

C stability from 0

◦

Cto

100

◦

C. In an article from ETH Zurich, a fractional-N digital

phase locked loop (DPLL) resolves the phase error in the

voltage domain, replacing the time-to-digital converter, with

a ramp generator and a digital-to-analog converter, increasing

its power supply and common-mode rejection ratios, achieving

101-fs rms jitter.

To address increasing demands on data bandwidth, Rambus

and the University of Alberta demonstrate a digital receiver for

112-Gb/s communication. A discrete-time front-end, 56GS/s

ADC, and DSP-based decision feedback equalizer plus

feed forward equalizer (DFE-FFE) can compensate 36 dB of

channel loss and operates over a wide range of data rates. For

memory interfaces, researchers at Seoul National University

improve four-level pulse-amplitude modulation (PAM-4) trans-

mitter linearity by adding calibration to an impedance-matched

voltage-mode driver; 28 Gb/s/pin is obtained at 0.64 pJ/bit.

Finally, the issue concludes with three wireless commu-

nications articles. For low duty cycle Internet of Things

(IoT) applications, low-power wake-up receivers can signif-

icantly reduce the energy to establish a link. Compatible with

BLE and Wi-Fi systems, a wake-up receiver from UCSD

can operate at 4.4 μW with strong interference resilience.

A second article from UCSD improves the sensitivity of

a frequency-shift keying (FSK) receiver using noncoherent

16-FSK to achieve a sensitivity of −103 dBm at 100 kb/s.

To increase the data throughput of 5G systems, a dual-

polarized multiple input multiple output (MIMO) operation

has been proposed. An analog-assisted cross-polarization leak-

age cancellation technique is implemented for a 28-GHz

phased-array beamformer to achieve more than 41-dB cross-

polarization isolation and is demonstrated in a 64-element

phased-array transceiver by the Tokyo Institute of Technology

and NEC Corporation.

This Special Issue required substantial efforts from the

authors and the reviewers to meet the high standards of quality

maintained by the journal. We would like to thank them for

their efforts. We would also like to thank the Japan/Far East

and North America/Europe Technical Program Committees

of the Symposium on VLSI Circuits for coordinating and

successfully running the conference, and for recommending

articles for this Special Issue. We highly appreciate their work

and the support of the Symposium Executive Committees.

Finally, we would like to thank the Journal Editor-in-Chief

Dr. Pavan Hanumolu for his guidance and the staff of the IEEE

RANSACTIONS and Journals Department for their invaluable

assistance in publishing this issue.

In closing, we encourage readers to attend the 2021 Sym-

posium on VLSI Circuits to be held June 13–19, 2021,

fully virtual. We also look forward to meeting you at future

Symposia once it is safe to resume in-person events. Please

visit the Symposium website, www.vlsisymposium.org, for

more details.

RIAN GINSBURG, Gu est Editor

Texas Instruments

Dallas, TX USA

e-mail: bginzz@ti.com

USUKE OIKE, Guest Editor

Sony Semiconductor Solutions

Kanagawa, Japan

e-mail: yusuke.oike@sony.com

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