################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA MPSoC_XCZU4EV驱动双路OV5640采集视频,TFT-LCD显示(Verilog HDL实现)
共807个文件
v:108个
xml:95个
txt:81个
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FPGA MPSoC XCZU2CG、XCZU2EG和XCZU4EV驱动程序。 基于Vivado Design Suite和Verilog HDL实现。 项目代码可顺利编译运行~
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FPGA MPSoC_XCZU4EV驱动双路OV5640采集视频,TFT-LCD显示(Verilog HDL实现) (807个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
bd_9054.bd 12KB
dual_ov5640_lcd.bit 7.44MB
bd_9054.bmm 688B
bd_9054.bxml 7KB
dual_ov5640_lcd_routed.dcp 12.65MB
dual_ov5640_lcd_placed.dcp 10.49MB
dual_ov5640_lcd_physopt.dcp 10.44MB
dual_ov5640_lcd_opt.dcp 8.11MB
dual_ov5640_lcd.dcp 5.8MB
ddr4_0_phy.dcp 1.06MB
ddr4_0_phy.dcp 1.06MB
ila_0.dcp 894KB
ila_0.dcp 886KB
ila_0.dcp 835KB
ila_0.dcp 833KB
ila_0.dcp 810KB
ila_0.dcp 799KB
ila_0.dcp 758KB
ila_0.dcp 755KB
ila_0.dcp 716KB
ila_0.dcp 706KB
ila_0.dcp 691KB
ila_0.dcp 683KB
ila_0.dcp 656KB
ila_0.dcp 610KB
ila_0.dcp 570KB
dbg_hub.dcp 372KB
dbg_hub.dcp 364KB
dbg_hub.dcp 353KB
dbg_hub.dcp 353KB
wr_fifo.dcp 221KB
wr_fifo.dcp 221KB
wr_fifo.dcp 220KB
compile.do 11KB
compile.do 10KB
compile.do 10KB
compile.do 10KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 993B
compile.do 993B
compile.do 979B
compile.do 979B
compile.do 763B
compile.do 739B
compile.do 698B
compile.do 688B
simulate.do 460B
simulate.do 452B
simulate.do 452B
simulate.do 333B
simulate.do 333B
elaborate.do 332B
simulate.do 326B
simulate.do 326B
simulate.do 326B
simulate.do 326B
simulate.do 303B
simulate.do 294B
simulate.do 294B
elaborate.do 205B
elaborate.do 205B
simulate.do 191B
simulate.do 191B
simulate.do 189B
simulate.do 187B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
simulate.do 11B
calibration_ddr.elf 91KB
mb_bootloop_le.elf 643B
mb_bootloop_le.elf 643B
run.f 9KB
run.f 9KB
run.f 839B
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