################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA MPSoC_XCZU2EG驱动OV5640采集视频,TFT-LCD显示(Verilog HDL实现)
共832个文件
v:119个
txt:83个
sv:62个
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FPGA MPSoC XCZU2CG、XCZU2EG和XCZU4EV驱动程序。 基于Vivado Design Suite和Verilog HDL实现。 项目代码可顺利编译运行~
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FPGA MPSoC_XCZU2EG驱动OV5640采集视频,TFT-LCD显示(Verilog HDL实现) (832个子文件)
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
bd_9054.bd 12KB
ov5640_lcd.bit 5.31MB
bd_9054.bmm 688B
bd_9054.bxml 7KB
ov5640_lcd_routed.dcp 11.39MB
ov5640_lcd_placed.dcp 9.49MB
ov5640_lcd_physopt.dcp 9.45MB
ov5640_lcd_opt.dcp 7.35MB
ov5640_lcd.dcp 5.32MB
design_1_axi_smc_2.dcp 2.29MB
design_1_axi_vdma_0_1.dcp 1.78MB
ddr4_0_phy.dcp 1.06MB
ddr4_0_phy.dcp 1.06MB
ddr4_0_phy.dcp 1.06MB
ddr4_0_phy.dcp 1.06MB
design_1_v_tc_0_0.dcp 634KB
ila_0.dcp 630KB
ila_0.dcp 629KB
ila_0.dcp 597KB
design_1_zynq_ultra_ps_e_0_2.dcp 415KB
design_1_clk_wiz_0_0.dcp 369KB
dbg_hub.dcp 364KB
dbg_hub.dcp 353KB
design_1_auto_pc_0.dcp 295KB
wr_fifo.dcp 220KB
design_1_v_axi4s_vid_out_0_0.dcp 200KB
design_1_v_vid_in_axi4s_0_0.dcp 172KB
design_1_xbar_0.dcp 140KB
design_1_axi_gpio_0_0.dcp 44KB
design_1_rst_ps8_0_99M_1.dcp 22KB
design_1_ov5640_capture_data_0_0.dcp 19KB
design_1_rgb2lcd_0_0.dcp 14KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
compile.do 10KB
compile.do 10KB
compile.do 10KB
compile.do 10KB
compile.do 1KB
compile.do 1KB
compile.do 1000B
compile.do 1000B
compile.do 949B
compile.do 949B
compile.do 935B
compile.do 935B
compile.do 748B
compile.do 724B
compile.do 683B
compile.do 673B
simulate.do 460B
simulate.do 452B
simulate.do 452B
simulate.do 333B
simulate.do 333B
elaborate.do 332B
simulate.do 326B
simulate.do 326B
simulate.do 326B
simulate.do 326B
simulate.do 303B
simulate.do 294B
simulate.do 294B
elaborate.do 205B
elaborate.do 205B
simulate.do 191B
simulate.do 191B
simulate.do 189B
simulate.do 187B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
simulate.do 11B
calibration_ddr.elf 91KB
mb_bootloop_le.elf 643B
mb_bootloop_le.elf 643B
run.f 8KB
run.f 8KB
run.f 795B
run.f 795B
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