################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA MPSoC_XCZU2EG驱动OV5640采集视频,PL以太网视频传输(Verilog HDL实现)
共430个文件
v:71个
xml:41个
vhdl:39个
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FPGA MPSoC_XCZU2EG驱动OV5640采集视频,PL以太网视频传输(Verilog HDL实现) (430个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
ov5640_udp_pc.bit 5.31MB
ov5640_udp_pc_routed.dcp 1.49MB
ov5640_udp_pc_physopt.dcp 1.27MB
ov5640_udp_pc_placed.dcp 1.27MB
ov5640_udp_pc_opt.dcp 1023KB
ov5640_udp_pc.dcp 364KB
async_fifo_1024x32b.dcp 138KB
async_fifo_1024x32b.dcp 138KB
async_fifo_1024x32b.dcp 137KB
async_fifo_1024x32b.dcp 137KB
async_fifo_1024x32b.dcp 137KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
compile.do 782B
compile.do 758B
compile.do 717B
compile.do 707B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 195B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
run.f 571B
run.f 555B
usage_statistics_webtalk.html 45KB
xsim.ini 26KB
vivado.jou 818B
vivado.jou 782B
vivado.jou 777B
vivado.jou 763B
vivado.jou 734B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 95KB
runme.log 55KB
runme.log 44KB
ip_upgrade.log 25KB
runme.log 24KB
runme.log 24KB
ov5640_udp_pc.lpr 343B
elab.opt 188B
vivado.pb 159KB
vivado.pb 88KB
vivado.pb 38KB
vivado.pb 38KB
place_design.pb 25KB
route_design.pb 18KB
opt_design.pb 14KB
init_design.pb 13KB
write_bitstream.pb 5KB
phys_opt_design.pb 2KB
ov5640_udp_pc_power_summary_routed.pb 740B
clk_wiz_0_utilization_synth.pb 222B
clk_wiz_utilization_synth.pb 222B
ov5640_udp_pc_utilization_placed.pb 222B
ov5640_udp_pc_utilization_synth.pb 222B
async_fifo_1024x32b_utilization_synth.pb 216B
vivado.pb 149B
ov5640_udp_pc_timing_summary_routed.pb 109B
ov5640_udp_pc_drc_routed.pb 74B
ov5640_udp_pc_methodology_drc_routed.pb 52B
ov5640_udp_pc_route_status.pb 44B
ov5640_udp_pc_drc_opted.pb 37B
ov5640_udp_pc_bus_skew_routed.pb 36B
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