################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA MPSoC_XCZU2CG驱动双路OV5640采集视频,HDMI显示(Verilog HDL实现)
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FPGA MPSoC XCZU2CG、XCZU2EG和XCZU4EV驱动程序。 基于Vivado Design Suite和Verilog HDL实现。 项目代码可顺利编译运行~
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FPGA MPSoC_XCZU2CG驱动双路OV5640采集视频,HDMI显示(Verilog HDL实现) (655个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
bd_9054.bd 12KB
top_dual_ov5640_hdmi.bit 5.31MB
bd_9054.bmm 730B
top_dual_ov5640_hdmi_routed.dcp 12.53MB
top_dual_ov5640_hdmi_placed.dcp 10.43MB
top_dual_ov5640_hdmi_physopt.dcp 10.38MB
top_dual_ov5640_hdmi_opt.dcp 8.07MB
ddr4_0.dcp 4.85MB
ddr4_0.dcp 4.84MB
ddr4_0_phy.dcp 1.06MB
ddr4_0_phy.dcp 1.06MB
top_dual_ov5640_hdmi.dcp 557KB
dbg_hub.dcp 354KB
dbg_hub.dcp 353KB
wr_fifo.dcp 221KB
rd_fifo.dcp 221KB
wr_fifo.dcp 220KB
rd_fifo.dcp 220KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
compile.do 7KB
compile.do 7KB
compile.do 7KB
compile.do 7KB
compile.do 1KB
compile.do 1KB
compile.do 986B
compile.do 986B
compile.do 935B
compile.do 935B
compile.do 921B
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compile.do 697B
compile.do 673B
compile.do 632B
compile.do 622B
simulate.do 460B
simulate.do 452B
simulate.do 452B
simulate.do 333B
simulate.do 333B
elaborate.do 332B
simulate.do 326B
simulate.do 326B
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simulate.do 326B
simulate.do 311B
simulate.do 306B
simulate.do 306B
elaborate.do 205B
elaborate.do 205B
simulate.do 195B
simulate.do 191B
simulate.do 191B
simulate.do 189B
elaborate.do 183B
wave.do 32B
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wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
simulate.do 11B
mb_bootloop_le.elf 643B
mb_bootloop_le.elf 643B
run.f 6KB
run.f 6KB
run.f 781B
run.f 781B
run.f 753B
run.f 753B
run.f 486B
run.f 470B
usage_statistics_webtalk.html 89KB
top_dual_ov5640_hdmi.hwdef 28KB
xsim.ini 26KB
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