################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA MPSoC_XCZU2EG实现以太网UDP通信(Verilog HDL实现)
共332个文件
v:44个
xml:40个
rst:24个
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FPGA MPSoC XCZU2CG、XCZU2EG和XCZU4EV驱动程序。 基于Vivado Design Suite和Verilog HDL实现。 项目代码可顺利编译运行~
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FPGA MPSoC_XCZU2EG实现以太网UDP通信(Verilog HDL实现) (332个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
eth_udp_loop.bit 5.31MB
eth_udp_loop_routed.dcp 1.21MB
eth_udp_loop_physopt.dcp 1.03MB
eth_udp_loop_placed.dcp 1.03MB
eth_udp_loop_opt.dcp 740KB
eth_udp_loop.dcp 308KB
sync_fifo_2048x32b.dcp 71KB
sync_fifo_2048x32b.dcp 71KB
sync_fifo_2048x32b.dcp 71KB
sync_fifo_2048x32b.dcp 71KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
clk_wiz.dcp 11KB
compile.do 772B
compile.do 748B
compile.do 707B
compile.do 697B
simulate.do 307B
simulate.do 300B
simulate.do 300B
simulate.do 191B
elaborate.do 179B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
run.f 561B
run.f 545B
usage_statistics_webtalk.html 41KB
xsim.ini 26KB
vivado.jou 805B
vivado.jou 771B
vivado.jou 767B
vivado.jou 742B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 71KB
runme.log 41KB
runme.log 35KB
runme.log 24KB
ip_upgrade.log 1KB
eth_udp_loop.lpr 343B
elab.opt 184B
vivado.pb 120KB
vivado.pb 67KB
vivado.pb 38KB
place_design.pb 24KB
route_design.pb 15KB
opt_design.pb 12KB
init_design.pb 5KB
write_bitstream.pb 3KB
phys_opt_design.pb 2KB
eth_udp_loop_power_summary_routed.pb 723B
clk_wiz_utilization_synth.pb 222B
eth_udp_loop_utilization_placed.pb 222B
eth_udp_loop_utilization_synth.pb 222B
sync_fifo_2048x32b_utilization_synth.pb 216B
vivado.pb 149B
eth_udp_loop_timing_summary_routed.pb 109B
eth_udp_loop_methodology_drc_routed.pb 52B
eth_udp_loop_route_status.pb 44B
eth_udp_loop_drc_routed.pb 37B
eth_udp_loop_drc_opted.pb 37B
eth_udp_loop_bus_skew_routed.pb 30B
vlog.prj 241B
eth_udp_loop_io_placed.rpt 261KB
eth_udp_loop_timing_summary_routed.rpt 128KB
eth_udp_loop_clock_utilization_routed.rpt 20KB
eth_udp_loop_utilization_placed.rpt 10KB
eth_udp_loop_control_sets_placed.rpt 10KB
eth_udp_loop_power_routed.rpt 10KB
eth_udp_loop_utilization_synth.rpt 7KB
sync_fifo_2048x32b_utilization_synth.rpt 6KB
clk_wiz_utilization_synth.rpt 6KB
eth_udp_loop_methodology_drc_routed.rpt 5KB
eth_udp_loop_drc_routed.rpt 1KB
eth_udp_loop_drc_opted.rpt 1KB
eth_udp_loop_bus_skew_routed.rpt 992B
eth_udp_loop_route_status.rpt 588B
eth_udp_loop_power_routed.rpx 646KB
eth_udp_loop_timing_summary_routed.rpx 105KB
eth_udp_loop_methodology_drc_routed.rpx 5KB
共 332 条
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