FPGA MPSoC_XCZU4EV驱动双目OV5640摄像头采集视频，LCD显示（VITIS实现）.zip

axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,D:/Xilinx_2019_2/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2/sim_tlm"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_v_mix_0_0/src"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/8f82/hdl/verilog" axi_vip_axi4pc.sv,systemverilog,xilinx_vip,D:/Xilinx_2019_2/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2/sim_tlm"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_v_mix_0_0/src"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/8f82/hdl/verilog" xil_common_vip_pkg.sv,systemverilog,xilinx_vip,D:/Xilinx_2019_2/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2/sim_tlm"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_v_mix_0_0/src"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/8f82/hdl/verilog" axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,D:/Xilinx_2019_2/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2/sim_tlm"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_v_mix_0_0/src"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/8f82/hdl/verilog" axi_vip_pkg.sv,systemverilog,xilinx_vip,D:/Xilinx_2019_2/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2/sim_tlm"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_v_mix_0_0/src"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/8f82/hdl/verilog" axi4stream_vip_if.sv,systemverilog,xilinx_vip,D:/Xilinx_2019_2/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_2/sim_tlm"incdir="../../../../dual_ov5640_lcd.srcs/sources_1/bd/design_