################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA MPSoC_XCZU4EV实现双路ADC驱动(Verilog HDL实现)
共380个文件
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v:41个
vh:36个
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FPGA MPSoC XCZU2CG、XCZU2EG和XCZU4EV驱动程序。 基于Vivado Design Suite和Verilog HDL实现。 项目代码可顺利编译运行~
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FPGA MPSoC_XCZU4EV实现双路ADC驱动(Verilog HDL实现) (380个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
hs_dual_ad.bit 7.44MB
hs_dual_ad_routed.dcp 2.2MB
hs_dual_ad_physopt.dcp 1.94MB
hs_dual_ad_placed.dcp 1.94MB
hs_dual_ad_opt.dcp 1.61MB
ila_0.dcp 672KB
ila_0.dcp 672KB
ila_0.dcp 669KB
ila_0.dcp 636KB
dbg_hub.dcp 353KB
hs_dual_ad.dcp 14KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
compile.do 778B
compile.do 776B
compile.do 754B
compile.do 752B
compile.do 713B
compile.do 711B
compile.do 703B
compile.do 701B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 303B
simulate.do 294B
simulate.do 294B
simulate.do 195B
simulate.do 187B
elaborate.do 183B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
run.f 565B
run.f 549B
run.f 483B
run.f 467B
usage_statistics_webtalk.html 151KB
usage_statistics_ext_labtool.html 3KB
hw_ila_data_1.ila 285KB
.xsim_webtallk.info 59B
xsim.ini 26KB
xsim.ini 26KB
vivado.jou 775B
vivado.jou 751B
vivado.jou 746B
vivado.jou 702B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
hw_ila_1.layout 247KB
runme.log 112KB
runme.log 43KB
runme.log 24KB
runme.log 22KB
labtool_webtalk.log 690B
hs_dual_ad.lpr 343B
hs_dual_ad.ltx 7KB
debug_nets.ltx 7KB
elab.opt 188B
elab.opt 180B
vivado.pb 32KB
place_design.pb 28KB
opt_design.pb 18KB
route_design.pb 16KB
write_bitstream.pb 7KB
init_design.pb 6KB
phys_opt_design.pb 2KB
messagePromote.pb 2KB
hs_dual_ad_power_summary_routed.pb 723B
clk_wiz_0_utilization_synth.pb 292B
hs_dual_ad_utilization_placed.pb 292B
ila_0_utilization_synth.pb 286B
hs_dual_ad_utilization_synth.pb 286B
vivado.pb 149B
hs_dual_ad_timing_summary_routed.pb 109B
hs_dual_ad_drc_routed.pb 75B
hs_dual_ad_methodology_drc_routed.pb 52B
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