################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA MPSoC_XCZU4EV实现IP核MMCM_PLL驱动(Verilog HDL实现)
共291个文件
v:24个
txt:24个
pb:21个
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FPGA MPSoC XCZU2CG、XCZU2EG和XCZU4EV驱动程序。 基于Vivado Design Suite和Verilog HDL实现。 项目代码可顺利编译运行~
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FPGA MPSoC_XCZU4EV实现IP核MMCM_PLL驱动(Verilog HDL实现) (291个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 1KB
simulate.bat 1KB
compile.bat 836B
runme.bat 229B
runme.bat 229B
runme.bat 229B
ip_clk_wiz.bit 7.44MB
xsim_1.c 18KB
xsim.dbg 11KB
ip_clk_wiz_routed.dcp 391KB
ip_clk_wiz_physopt.dcp 389KB
ip_clk_wiz_placed.dcp 382KB
ip_clk_wiz_opt.dcp 378KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 12KB
ip_clk_wiz.dcp 8KB
compile.do 694B
compile.do 670B
compile.do 629B
compile.do 619B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 195B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 567KB
run.f 481B
run.f 465B
usage_statistics_webtalk.html 31KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
xsim.ini 26KB
xsim.ini 26KB
xsimSettings.ini 1KB
webtalk_20136.backup.jou 858B
webtalk.jou 858B
webtalk_35656.backup.jou 858B
webtalk_19612.backup.jou 858B
webtalk_20960.backup.jou 858B
webtalk_20332.backup.jou 858B
vivado.jou 748B
vivado.jou 744B
vivado.jou 731B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 29KB
runme.log 25KB
runme.log 19KB
webtalk_20332.backup.log 1KB
webtalk_19612.backup.log 1KB
webtalk_35656.backup.log 1KB
webtalk.log 1KB
webtalk_20136.backup.log 1KB
webtalk_20960.backup.log 1KB
xvlog.log 1KB
compile.log 1KB
elaborate.log 1023B
xsimkernel.log 330B
simulate.log 50B
xsimcrash.log 0B
ip_clk_wiz.lpr 343B
xsim.mem 28KB
xsim_0.win64.obj 581KB
xsim_1.win64.obj 13KB
elab.opt 188B
vivado.pb 39KB
vivado.pb 29KB
route_design.pb 14KB
opt_design.pb 11KB
place_design.pb 7KB
phys_opt_design.pb 7KB
init_design.pb 5KB
write_bitstream.pb 3KB
xelab.pb 2KB
xvlog.pb 2KB
ip_clk_wiz_power_summary_routed.pb 726B
clk_wiz_0_utilization_synth.pb 292B
ip_clk_wiz_utilization_placed.pb 292B
ip_clk_wiz_utilization_synth.pb 286B
vivado.pb 149B
ip_clk_wiz_timing_summary_routed.pb 70B
ip_clk_wiz_methodology_drc_routed.pb 52B
ip_clk_wiz_route_status.pb 43B
ip_clk_wiz_drc_routed.pb 37B
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