SH-4 CPU Core Architecture

Last updated 12 September 2002 2:29

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STMicroelectronics and Hitachi, Ltd.

ADCS 7182230F SH-4 CPU Core Architecture

SH-4 CPU Core

Architecture

ii

PRELIMINARY DATA

STMicroelectronics and Hitachi, Ltd.

SH-4 CPU Core Architecture ADCS 7182230F

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PRELIMINARY DATA

STMicroelectronics and Hitachi, Ltd.

ADCS 7182230F SH-4 CPU Core Architecture

Contents

Preface xi

1 Overview 15

1.1 SH-4 CPU core features 15

2.5 Memory-mapped registers 36

2.6 Data format in registers 37

2.7 Data formats in memory 37

2.8 Processor states 38

2.8.1 Reset state 38

2.8.2 Exception-handling state 38

2.8.3 Program execution state 38

2.8.4 Power-down state 39

2.9 Processor modes 40

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STMicroelectronics and Hitachi, Ltd.

SH-4 CPU Core Architecture ADCS 7182230F

3 Memory management unit (MMU) 41

3.3.4 TLB exception address register (TEA) 47

3.3.5 MMU control register (MMUCR) 47

3.4 Address space 51

3.4.1 Physical address space 51

3.4.2 External memory space 52

3.4.3 Virtual address space 55

3.4.4 On-chip RAM space 56

3.4.5 Address translation 57

3.4.6 Single virtual memory mode and multiple virtual memory

mode 57

3.6.1 MMU hardware management 62

3.6.2 MMU software management 62

3.6.3 MMU instruction (LDTLB) 63

3.6.4 Hardware ITLB miss handling 64

3.6.5 Avoiding synonym problems 64

3.7 Handling MMU exceptions 65

3.7.1 ITLBMULTIHIT 65

3.7.2 ITLBMISS 65

3.7.3 EXECPROT 66

v

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STMicroelectronics and Hitachi, Ltd.

ADCS 7182230F SH-4 CPU Core Architecture

3.7.4 OTLBMULTIHIT 67

3.8.3 UTLB address array 72

3.8.4 UTLB data array 1 74

4 Caches 75

4.1 Overview 75

4.1.1 Features 75

4.2 Register descriptions 77

4.2.1 Cache control register (CCR) 77

4.2.2 Queue address control register 0 (QACR0) 80

4.2.3 Queue address control register 1 (QACR1) 81

4.3 Operand cache (OC) 82

4.3.1 Configuration 82

4.4.1 Configuration 92

4.4.2 Read operation 94

4.4.3 IC index mode 94